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author | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-30 20:46:12 -0700 |
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committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-30 20:46:12 -0700 |
commit | 4cfdce39025d0b1946b7d04ed9229330aa1d8649 (patch) | |
tree | 3de3740fa0d9f336792f289aa05bf95d2f204cfb /parse-opcodes | |
parent | f4d33eb18c572893ab0519999365ac4b196b2c27 (diff) | |
download | riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.zip riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.tar.gz riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.tar.bz2 |
Add logical shifts to follow spec
Diffstat (limited to 'parse-opcodes')
-rwxr-xr-x | parse-opcodes | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/parse-opcodes b/parse-opcodes index c09ee59..7618dc4 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -953,7 +953,7 @@ def make_latex_table(): def make_vector_adoc_table(): #print_vec_subtitile('RV32V Standard Extension') print_vec_header() - print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor', 'vneg') + print_vec_insts('vadd', 'vsub', 'vsl', 'vsrl', 'vsra', 'vand', 'vor', 'vxor', 'vneg') print_vec_insts('vseq', 'vsne', 'vslt', 'vsge', 'vsltu', 'vsgeu') print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide', 'vrgather') print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') |