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author | Andrew Waterman <andrew@sifive.com> | 2017-04-25 11:35:04 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-04-25 11:36:57 -0700 |
commit | 03c186e1197a574cd777d37c949039cf9e82dd76 (patch) | |
tree | 5af71d628244b3488acd6095accdad5b4f8af141 /opcodes | |
parent | e4c935733f653d97913fb0418abfa89f6f3d90d2 (diff) | |
download | riscv-opcodes-03c186e1197a574cd777d37c949039cf9e82dd76.zip riscv-opcodes-03c186e1197a574cd777d37c949039cf9e82dd76.tar.gz riscv-opcodes-03c186e1197a574cd777d37c949039cf9e82dd76.tar.bz2 |
Remove hret instruction
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -117,7 +117,6 @@ ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 uret 11..7=0 19..15=0 31..20=0x002 14..12=0 6..2=0x1C 1..0=3 sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 -hret 11..7=0 19..15=0 31..20=0x202 14..12=0 6..2=0x1C 1..0=3 mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 |