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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-09 17:08:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-02-09 17:09:49 -0800 |
| commit | c7159b644a01c56851150b216c6fe2e2a730595e (patch) | |
| tree | 33e15eff0f6fdee36a45823465c38c31186963de /opcodes-v | |
| parent | 19d6c637d1aeffd59dc08499d515061659cba1ad (diff) | |
| download | riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.zip riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.tar.gz riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.tar.bz2 | |
Updates from most recent meeting
Diffstat (limited to 'opcodes-v')
| -rw-r--r-- | opcodes-v | 10 |
1 files changed, 6 insertions, 4 deletions
@@ -25,7 +25,6 @@ vamomax m vd vs3 vs2 19..15=0x14 26..25=3 14=1 6..0=0x27 # First, all the immediates. vaddi m vd vs1 vimm 31..28=0 14=1 6..0=0x67 vsli m vd vs1 vimm 31..28=1 14=1 6..0=0x67 -vcvti m vd vs1 vimm 31..28=2 14=1 6..0=0x67 vclipi m vd vs1 vimm 31..28=3 14=1 6..0=0x67 vxori m vd vs1 vimm 31..28=4 14=1 6..0=0x67 vsri m vd vs1 vimm 31..28=5 14=1 6..0=0x67 @@ -54,13 +53,16 @@ vsge m vd vs1 vs2 27..25=7 31..28=9 14=1 6..0=0x67 # group 31..28=10 includes instructions that write xd # (and may also read xs1 and/or xs2). -vextract m rd vs1 rs2 27..25=1 31..28=10 14=1 6..0=0x67 +vextract m rd vs1 rs2 27..25=0 31..28=10 14=1 6..0=0x67 +vmfirst m rd vs1 27..25=7 31..28=10 14=1 6..0=0x67 24..20=0 +vmpop m rd vs1 27..25=7 31..28=10 14=1 6..0=0x67 24..20=1 # group 31..28=11 includes instructions that read xs1 and/or xs2, # but do not write xd. vclip m vd vs1 rs2 27..25=0 31..28=11 14=1 6..0=0x67 -vinsert m vd rs1 rs2 27..25=1 31..28=11 14=1 6..0=0x67 -vslide m vd rs1 rs2 27..25=2 31..28=11 14=1 6..0=0x67 +vcvt m vd vs1 rs2 27..25=1 31..28=11 14=1 6..0=0x67 +vslide m vd vs1 rs2 27..25=2 31..28=11 14=1 6..0=0x67 +vinsert m vd rs1 rs2 27..25=4 31..28=11 14=1 6..0=0x67 # group 31..28=12 vxor m vd vs1 vs2 27..25=0 31..28=12 14=1 6..0=0x67 |