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author | Torbjørn <tovine@users.noreply.github.com> | 2019-04-23 18:44:05 +0200 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2019-04-23 09:44:05 -0700 |
commit | 308d16c30acd86f6814ef12cbc0e507a8c588f4e (patch) | |
tree | 5795a6ef167c800c3892bc00475bdc833740bb46 | |
parent | 6ddb1558424774bc7d0695632291df6c32aae8f5 (diff) | |
download | riscv-opcodes-308d16c30acd86f6814ef12cbc0e507a8c588f4e.zip riscv-opcodes-308d16c30acd86f6814ef12cbc0e507a8c588f4e.tar.gz riscv-opcodes-308d16c30acd86f6814ef12cbc0e507a8c588f4e.tar.bz2 |
Updated path to FESVR_H in Makefile (#25)
-rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -2,7 +2,7 @@ SHELL := /bin/sh ISASIM_H := ../riscv-isa-sim/riscv/encoding.h PK_H := ../riscv-pk/machine/encoding.h -FESVR_H := ../riscv-fesvr/fesvr/encoding.h +FESVR_H := ../riscv-isa-sim/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h |