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author | Andrew Waterman <andrew@sifive.com> | 2019-06-16 14:38:30 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-06-16 14:38:30 -0700 |
commit | e7efefd3326e3e73d2063718820f2966113f0516 (patch) | |
tree | b72adc04c179b8610ce1e7acf032bcc9b1c798ef | |
parent | 0c06e7381689977480fd9ec6a1711f8eb48c6382 (diff) | |
download | riscv-opcodes-e7efefd3326e3e73d2063718820f2966113f0516.zip riscv-opcodes-e7efefd3326e3e73d2063718820f2966113f0516.tar.gz riscv-opcodes-e7efefd3326e3e73d2063718820f2966113f0516.tar.bz2 |
Updates for hypervisor v0.4
-rwxr-xr-x | parse-opcodes | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/parse-opcodes b/parse-opcodes index 1bd628a..4590fff 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -131,19 +131,20 @@ csrs = [ (0x180, 'satp'), # Standard Hypervisor R/w - (0x200, 'bsstatus'), - (0x204, 'bsie'), - (0x205, 'bstvec'), - (0x240, 'bsscratch'), - (0x241, 'bsepc'), - (0x242, 'bscause'), - (0x243, 'bstval'), - (0x244, 'bsip'), - (0x280, 'bsatp'), - (0xA00, 'hstatus'), - (0xA02, 'hedeleg'), - (0xA03, 'hideleg'), - (0xA80, 'hgatp'), + (0x200, 'vsstatus'), + (0x204, 'vsie'), + (0x205, 'vstvec'), + (0x240, 'vsscratch'), + (0x241, 'vsepc'), + (0x242, 'vscause'), + (0x243, 'vstval'), + (0x244, 'vsip'), + (0x280, 'vsatp'), + (0x600, 'hstatus'), + (0x602, 'hedeleg'), + (0x603, 'hideleg'), + (0x606, 'hcounteren'), + (0x680, 'hgatp'), # Tentative CSR assignment for CLIC (0x007, 'utvt'), |