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author | Andrew Waterman <andrew@sifive.com> | 2020-02-28 14:09:41 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-02-28 14:09:41 -0800 |
commit | d8ad9ffe05f4c1035180f0ed8136a3cb48e6f0ae (patch) | |
tree | 21e691224319cbf3f61adb5146aff4c7a27930e0 | |
parent | dd55202ca3e8b36e34510a09e94b0046416723fe (diff) | |
download | riscv-opcodes-d8ad9ffe05f4c1035180f0ed8136a3cb48e6f0ae.zip riscv-opcodes-d8ad9ffe05f4c1035180f0ed8136a3cb48e6f0ae.tar.gz riscv-opcodes-d8ad9ffe05f4c1035180f0ed8136a3cb48e6f0ae.tar.bz2 |
Add mcountinhibit CSR
-rwxr-xr-x | parse_opcodes | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/parse_opcodes b/parse_opcodes index 6ee7a5c..59b9bff 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -175,6 +175,7 @@ csrs = [ (0x304, 'mie'), (0x305, 'mtvec'), (0x306, 'mcounteren'), + (0x320, 'mcountinhibit'), (0x340, 'mscratch'), (0x341, 'mepc'), (0x342, 'mcause'), |