revamp hwacha-v3 opcodes

3 files changed, 115 insertions, 116 deletions

diff --git a/opcodes-hwacha b/opcodes-hwacha
index c8718b4..57d798d 100644
--- a/opcodes-hwacha
+++ b/opcodes-hwacha
@@ -1,124 +1,78 @@
 # vector scalar instructions
-stop    31..27=0 26..22=0 21..17=0 16..10=0 9..7=5 6..2=0x1D 1..0=3
-utidx   rd       26..22=0 21..17=0 16..10=0 9..7=6 6..2=0x1D 1..0=3
-movz    rd       rs1      rs2      16..10=0 9..7=7 6..2=0x1D 1..0=3
-movn    rd       rs1      rs2      16..10=1 9..7=7 6..2=0x1D 1..0=3
-fmovz   rd       rs1      rs2      16..10=2 9..7=7 6..2=0x1D 1..0=3
-fmovn   rd       rs1      rs2      16..10=3 9..7=7 6..2=0x1D 1..0=3
+stop    31..25=0 24..20=0 19..15=0 14..12=5 11..7=0 6..2=0x1D 1..0=3
+utidx   31..25=0 24..20=0 19..15=0 14..12=6 rd      6..2=0x1D 1..0=3
+movz    31..25=0 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
+movn    31..25=1 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
+fmovz   31..25=2 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
+fmovn   31..25=3 rs2      rs1      14..12=7 rd      6..2=0x1D 1..0=3
 
-# vector instructions
-vsetcfgvl    rd       rs1      rs2      acclimm7                         9=1 8=1 7=1 6..2=0x02 1..0=3
-vsetvl       rd       rs1      21..17=0 16..10=0                         9=1 8=1 7=0 6..2=0x02 1..0=3
-vmvv         rd       rs1      21..17=0 16..10=1                         9=1 8=1 7=0 6..2=0x02 1..0=3
-vgetcfg      rd       26..22=0 21..17=0 16..10=0                         9=1 8=0 7=0 6..2=0x02 1..0=3
-vgetvl       rd       26..22=0 21..17=0 16..10=1                         9=1 8=0 7=0 6..2=0x02 1..0=3
-vf           imm12hi  rs1      21..17=0 imm12lo                          9=0 8=1 7=0 6..2=0x02 1..0=3
-
-# vector supervisor instructions
-vxcptsave    31..27=0 rs1      21..17=0 16..10=0                         9=0 8=1 7=1 6..2=0x02 1..0=3
-vxcptrestore 31..27=0 rs1      21..17=0 16..10=1                         9=0 8=1 7=1 6..2=0x02 1..0=3
-vxcptkill    31..27=0 26..22=0 21..17=0 16..10=2                         9=0 8=1 7=1 6..2=0x02 1..0=3
+# rocc format, xd = inst[14], xs1 = inst[13], xs2 = inst[12]
 
-vxcptevac    31..27=0 rs1      21..17=0 16..10=3                         9=0 8=1 7=1 6..2=0x02 1..0=3
-vxcpthold    31..27=0 26..22=0 21..17=0 16..10=4                         9=0 8=1 7=1 6..2=0x02 1..0=3
-venqcmd      31..27=0 rs1      rs2      16..10=5                         9=0 8=1 7=1 6..2=0x02 1..0=3
-venqimm1     31..27=0 rs1      rs2      16..10=6                         9=0 8=1 7=1 6..2=0x02 1..0=3
-venqimm2     31..27=0 rs1      rs2      16..10=7                         9=0 8=1 7=1 6..2=0x02 1..0=3
-venqcnt      31..27=0 rs1      rs2      16..10=8                         9=0 8=1 7=1 6..2=0x02 1..0=3
-
-#                                                        3=d
-#                                                        2=w
-#                                1=st          1=f  1=u  1=h      0   1   1=strided
-#                                0=ld          0=x  0=s  0=b      0   1   0=unit-strided
-#                                ---------------------------------------------------
-#                                mem  padding  x/f  u/s  width    xd  xs1 xs2 opcode
-# unit-strided vector load       |    |        |    |    |        |   |   |   |
-#                                |    |        |    |    |        |   |   |   |
-vld         rd      rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlw         rd      rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlwu        rd      rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlh         rd      rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlhu        rd      rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlb         rd      rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
-vlbu        rd      rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
-vfld        rd      rs1 21..17=0 16=0 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
-vflw        rd      rs1 21..17=0 16=0 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
+# vector instructions
+vsetcfg      imm12             rs1      14=0 13=1 12=0 11..7=0 6..2=0x02 1..0=3
+vsetvl       31..25=0 24..20=0 rs1      14=1 13=1 12=0 rd      6..2=0x02 1..0=3
+vgetcfg      31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3
+vgetvl       31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd      6..2=0x02 1..0=3
 
-#                                mem  padding  x/f  u/s  width    xd  xs1 xs2 opcode
-# strided vector load            |    |        |    |    |        |   |   |   |
-#                                |    |        |    |    |        |   |   |   |
-vlstd       rd      rs1 rs2      16=0 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlstw       rd      rs1 rs2      16=0 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlstwu      rd      rs1 rs2      16=0 15..14=0 13=0 12=1 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlsth       rd      rs1 rs2      16=0 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlsthu      rd      rs1 rs2      16=0 15..14=0 13=0 12=1 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlstb       rd      rs1 rs2      16=0 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
-vlstbu      rd      rs1 rs2      16=0 15..14=0 13=0 12=1 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
-vflstd      rd      rs1 rs2      16=0 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
-vflstw      rd      rs1 rs2      16=0 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
+vmvv         31..25=1 24..20=0 rs1      14=0 13=0 12=0 rd      6..2=0x03 1..0=3
+vmsv         31..25=1 24..20=0 rs1      14=0 13=1 12=0 rd      6..2=0x03 1..0=3
+vf           imm12hi  24..20=1 rs1      14=0 13=1 12=0 imm12lo 6..2=0x03 1..0=3
 
-#                                segment       x/f  u/s  width    xd  xs1 xs2 opcode
-# segmented vector load          |             |    |    |        |   |   |   |
-#                                |             |    |    |        |   |   |   |
-vlsegd      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlsegw      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlsegwu     rd      rs1 21..17=0 vseglen       13=0 12=1 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlsegh      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlseghu     rd      rs1 21..17=0 vseglen       13=0 12=1 11..10=1 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlsegb      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x16 1..0=3
-vlsegbu     rd      rs1 21..17=0 vseglen       13=0 12=1 11..10=0 9=0 8=1 7=0 6..2=0x16 1..0=3
-vflsegd     rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x16 1..0=3
-vflsegw     rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
+# vector supervisor instructions
+vxcptsave    31..25=0 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+vxcptrestore 31..25=1 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+vxcptkill    31..25=2 24..20=0 19..15=0 14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
 
-#                                segment       x/f  u/s  width    xd  xs1 xs2 opcode
-# segmented strided vector load  |             |    |    |        |   |   |   |
-#                                |             |    |    |        |   |   |   |
-vlsegstd    rd      rs1 rs2      vseglen       13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegstw    rd      rs1 rs2      vseglen       13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegstwu   rd      rs1 rs2      vseglen       13=0 12=1 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegsth    rd      rs1 rs2      vseglen       13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegsthu   rd      rs1 rs2      vseglen       13=0 12=1 11..10=1 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegstb    rd      rs1 rs2      vseglen       13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x16 1..0=3
-vlsegstbu   rd      rs1 rs2      vseglen       13=0 12=1 11..10=0 9=0 8=1 7=1 6..2=0x16 1..0=3
-vflsegstd   rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x16 1..0=3
-vflsegstw   rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
+vxcptevac    31..25=3 24..20=0 rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+vxcpthold    31..25=4 24..20=0 19..15=0 14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+venqcmd      31..25=5 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+venqimm1     31..25=6 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+venqimm2     31..25=7 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
+venqcnt      31..25=8 rs2      rs1      14=0 13=1 12=1 11..7=0 6..2=0x03 1..0=3
 
-#                                mem  padding  x/f  u/s  width    xd  xs1 xs2 opcode
-# unit-strided vector store      |    |        |    |    |        |   |   |   |
-#                                |    |        |    |    |        |   |   |   |
-vsd         rd      rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
-vsw         rd      rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
-vsh         rd      rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
-vsb         rd      rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
-vfsd        rd      rs1 21..17=0 16=1 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
-vfsw        rd      rs1 21..17=0 16=1 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
+#                              3=d
+#                              2=w
+#                    1=f  1=u  1=h                   0    1    1=strided
+#           3-bits   0=x  0=s  0=b                   0    1    0=unit-strided
+#           ---------------------------------------------------------------------------
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vlsegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlsegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlsegwu     vseglen  28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlsegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlseghu     vseglen  28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlsegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlsegbu     vseglen  28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vflsegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vflsegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
 
-#                                mem  padding  x/f  u/s  width    xd  xs1 xs2 opcode
-# strided vector store           |    |        |    |    |        |   |   |   |
-#                                |    |        |    |    |        |   |   |   |
-vsstd       rd      rs1 rs2      16=1 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
-vsstw       rd      rs1 rs2      16=1 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
-vssth       rd      rs1 rs2      16=1 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
-vsstb       rd      rs1 rs2      16=1 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
-vfsstd      rd      rs1 rs2      16=1 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
-vfsstw      rd      rs1 rs2      16=1 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vlsegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegstwu   vseglen  28=0 27=1 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegsthu   vseglen  28=0 27=1 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsegstbu   vseglen  28=0 27=1 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vflsegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vflsegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
 
-#                                segment       x/f  u/s  width    xd  xs1 xs2 opcode
-# segmented vector store         |             |    |    |        |   |   |   |
-#                                |             |    |    |        |   |   |   |
-vssegd      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x1E 1..0=3
-vssegw      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x1E 1..0=3
-vssegh      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x1E 1..0=3
-vssegb      rd      rs1 21..17=0 vseglen       13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x1E 1..0=3
-vfssegd     rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x1E 1..0=3
-vfssegw     rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x1E 1..0=3
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vssegd      vseglen  28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vssegw      vseglen  28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vssegh      vseglen  28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vssegb      vseglen  28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vfssegd     vseglen  28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vfssegw     vseglen  28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
 
-#                                segment       x/f  u/s  width    xd  xs1 xs2 opcode
-# segmented strided vector store |             |    |    |        |   |   |   |
-#                                |             |    |    |        |   |   |   |
-vssegstd    rd      rs1 rs2      vseglen       13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x1E 1..0=3
-vssegstw    rd      rs1 rs2      vseglen       13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x1E 1..0=3
-vssegsth    rd      rs1 rs2      vseglen       13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x1E 1..0=3
-vssegstb    rd      rs1 rs2      vseglen       13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x1E 1..0=3
-vfssegstd   rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x1E 1..0=3
-vfssegstw   rd      rs1 21..17=0 vseglen       13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x1E 1..0=3
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vssegstd    vseglen  28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vssegstw    vseglen  28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vssegsth    vseglen  28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vssegstb    vseglen  28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vfssegstd   vseglen  28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vfssegstw   vseglen  28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
diff --git a/opcodes-hwacha-pseudo b/opcodes-hwacha-pseudo
new file mode 100644
index 0000000..ec70cfd
--- /dev/null
+++ b/opcodes-hwacha-pseudo
@@ -0,0 +1,46 @@
+#                              3=d
+#                              2=w
+#                    1=f  1=u  1=h                   0    1    1=strided
+#           3-bits   0=x  0=s  0=b                   0    1    0=unit-strided
+#           ---------------------------------------------------------------------------
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vld         31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlw         31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlwu        31..29=0 28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlh         31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlhu        31..29=0 28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlb         31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vlbu        31..29=0 28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vfld        31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+vflw        31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vlstd       31..29=0 28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlstw       31..29=0 28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlstwu      31..29=0 28=0 27=1 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsth       31..29=0 28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlsthu      31..29=0 28=0 27=1 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlstb       31..29=0 28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vlstbu      31..29=0 28=0 27=1 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vflstd      31..29=0 28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+vflstw      31..29=0 28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vsd         31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vsw         31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vsh         31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vsb         31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vfsd        31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+vfsw        31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+
+#           segment  x/f  s/u  width                 xd   xs1  xs2     opcode
+#           |        |    |    |                     |    |    |       |
+vsstd       31..29=0 28=0 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vsstw       31..29=0 28=0 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vssth       31..29=0 28=0 27=0 26..25=1 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vsstb       31..29=0 28=0 27=0 26..25=0 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vfsstd      31..29=0 28=1 27=0 26..25=3 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+vfsstw      31..29=0 28=1 27=0 26..25=2 rs2      rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 61eae55..d46861d 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -27,8 +27,7 @@ arglut['imm12lo'] = (11,7)
 arglut['bimm12lo'] = (11,7)
 arglut['shamt'] = (25,20)
 arglut['shamtw'] = (24,20)
-arglut['acclimm7'] = (26,20)
-arglut['vseglen'] = (26,24)
+arglut['vseglen'] = (31,29)
 
 arglut['crd'] = (9,5)
 arglut['crs2'] = (9,5)