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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-02-02 01:31:07 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-02-02 01:31:07 -0800 |
| commit | 2fa0b5276db46e12110b6996e03b5aad694cf419 (patch) | |
| tree | 2539368ea1c87f26c36a87a8f1ace90abd2c5470 | |
| parent | 461bbedb2105312f055178346a588194fad9acec (diff) | |
| download | riscv-opcodes-2fa0b5276db46e12110b6996e03b5aad694cf419.zip riscv-opcodes-2fa0b5276db46e12110b6996e03b5aad694cf419.tar.gz riscv-opcodes-2fa0b5276db46e12110b6996e03b5aad694cf419.tar.bz2 | |
[opcodes,pk,sim,xcc] synci now bombs whole icache
| -rw-r--r-- | inst.v | 2 | ||||
| -rw-r--r-- | instr-table.tex | 18 | ||||
| -rw-r--r-- | opcodes | 2 |
3 files changed, 11 insertions, 11 deletions
@@ -59,7 +59,6 @@ `define L_BU 32'b?????_?????_????????????_100_0000011 `define L_HU 32'b?????_?????_????????????_101_0000011 `define L_WU 32'b?????_?????_????????????_110_0000011 -`define SYNCI 32'b00000_?????_????????????_111_0000011 `define S_B 32'b?????_?????_?????_???????_000_0100011 `define S_H 32'b?????_?????_?????_???????_001_0100011 `define S_W 32'b?????_?????_?????_???????_010_0100011 @@ -81,6 +80,7 @@ `define AMOMINU_D 32'b?????_?????_?????_00001_100_11_1000011 `define AMOMAXU_D 32'b?????_?????_?????_00001_110_11_1000011 `define RDNPC 32'b?????_00000_00000_0000000000_0010111 +`define SYNCI 32'b00000_00000_00000_0000000001_0010111 `define SYNC 32'b00000_00000_00000_0000000010_0010111 `define SYSCALL 32'b00000_00000_????????????_011_0010111 `define EI 32'b?????_00000_00000_0000000000_1111111 diff --git a/instr-table.tex b/instr-table.tex index 62ed2b8..a1d8b07 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -629,15 +629,6 @@ & \multicolumn{1}{|c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{4}{c|}{imm12} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & SYNCI rs1,imm12 \\ -\cline{2-10} - - -& -\multicolumn{1}{|c|}{0000000} & -\multicolumn{2}{c|}{000} & \multicolumn{3}{c|}{imm12hi} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & @@ -849,6 +840,15 @@ \multicolumn{5}{c|}{0000000000} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & SYNCI \\ +\cline{2-10} + + +& +\multicolumn{1}{|c|}{0000000} & +\multicolumn{5}{c|}{0000000000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{00000} & SYNC \\ \cline{2-10} @@ -78,7 +78,6 @@ l.d rd rs1 imm12 9..7=3 6..2=0x00 1..0=3 l.bu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3 l.hu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3 l.wu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3 -synci 31..27=0 rs1 imm12 9..7=7 6..2=0x00 1..0=3 # NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c # and elfxx-mips.c to detect them. this is a hack to handle the split immed. @@ -107,6 +106,7 @@ amominu.d rd rs1 rs2 16..10=6 9..7=3 6..2=0x10 1..0=3 amomaxu.d rd rs1 rs2 16..10=7 9..7=3 6..2=0x10 1..0=3 rdnpc rd 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x05 1..0=3 +synci 31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x05 1..0=3 sync 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x05 1..0=3 syscall 31..27=0 26..22=0 imm12 9..7=3 6..2=0x05 1..0=3 |