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| author | Quan Nguyen <quannguyen@berkeley.edu> | 2013-11-24 22:02:14 -0800 |
|---|---|---|
| committer | Quan Nguyen <quannguyen@berkeley.edu> | 2013-11-24 22:02:14 -0800 |
| commit | 128c2b7ef1790b39dc43b5aa2b0876becff01440 (patch) | |
| tree | 853ffc5cdd262a332e54780bef82d1ed054225b6 | |
| parent | f8e8b19f0bed6d03910e507760eabb10e3727693 (diff) | |
| download | riscv-opcodes-128c2b7ef1790b39dc43b5aa2b0876becff01440.zip riscv-opcodes-128c2b7ef1790b39dc43b5aa2b0876becff01440.tar.gz riscv-opcodes-128c2b7ef1790b39dc43b5aa2b0876becff01440.tar.bz2 | |
Add line in Makefile to parse confprec
| -rw-r--r-- | Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -7,6 +7,7 @@ install: $(ISASIM_H) $(PK_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex $(ISASIM_H): opcodes parse-opcodes ./parse-opcodes -isasim < $< > $@ + ./parse-opcodes -isasim < opcodes-hwacha-ut > ../riscv-isa-sim/hwacha/opcodes_hwacha_ut_half.h $(PK_H): opcodes parse-opcodes ./parse-opcodes -disasm < $< > $@ |