From be9b242d95f3ec5f044b7455fa9f32e2e8c55118 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 26 Jul 2013 04:39:25 -0700
Subject: Rip out Hwacha for now

---
 riscv/disasm.cc            | 70 ------------------------------------
 riscv/insns/fmovn.h        |  2 --
 riscv/insns/fmovz.h        |  2 --
 riscv/insns/movn.h         |  2 --
 riscv/insns/movz.h         |  2 --
 riscv/insns/stop.h         |  3 --
 riscv/insns/utidx.h        |  2 --
 riscv/insns/venqcmd.h      |  0
 riscv/insns/venqcnt.h      |  0
 riscv/insns/venqimm1.h     |  0
 riscv/insns/venqimm2.h     |  0
 riscv/insns/vf.h           |  9 -----
 riscv/insns/vfld.h         |  3 --
 riscv/insns/vflsegd.h      |  0
 riscv/insns/vflsegstd.h    |  0
 riscv/insns/vflsegstw.h    |  0
 riscv/insns/vflsegw.h      |  0
 riscv/insns/vflstd.h       |  3 --
 riscv/insns/vflstw.h       |  3 --
 riscv/insns/vflw.h         |  3 --
 riscv/insns/vfmst.h        |  4 ---
 riscv/insns/vfmsv.h        |  5 ---
 riscv/insns/vfmts.h        |  4 ---
 riscv/insns/vfmvv.h        |  5 ---
 riscv/insns/vfsd.h         |  3 --
 riscv/insns/vfssegd.h      |  0
 riscv/insns/vfssegstd.h    |  0
 riscv/insns/vfssegstw.h    |  0
 riscv/insns/vfssegw.h      |  0
 riscv/insns/vfsstd.h       |  3 --
 riscv/insns/vfsstw.h       |  3 --
 riscv/insns/vfsw.h         |  3 --
 riscv/insns/vlb.h          |  2 --
 riscv/insns/vlbu.h         |  2 --
 riscv/insns/vld.h          |  3 --
 riscv/insns/vlh.h          |  2 --
 riscv/insns/vlhu.h         |  2 --
 riscv/insns/vlsegb.h       |  0
 riscv/insns/vlsegbu.h      |  0
 riscv/insns/vlsegd.h       |  0
 riscv/insns/vlsegh.h       |  0
 riscv/insns/vlseghu.h      |  0
 riscv/insns/vlsegstb.h     |  0
 riscv/insns/vlsegstbu.h    |  0
 riscv/insns/vlsegstd.h     |  0
 riscv/insns/vlsegsth.h     |  0
 riscv/insns/vlsegsthu.h    |  0
 riscv/insns/vlsegstw.h     |  0
 riscv/insns/vlsegstwu.h    |  0
 riscv/insns/vlsegw.h       |  0
 riscv/insns/vlsegwu.h      |  0
 riscv/insns/vlstb.h        |  2 --
 riscv/insns/vlstbu.h       |  2 --
 riscv/insns/vlstd.h        |  3 --
 riscv/insns/vlsth.h        |  2 --
 riscv/insns/vlsthu.h       |  2 --
 riscv/insns/vlstw.h        |  2 --
 riscv/insns/vlstwu.h       |  2 --
 riscv/insns/vlw.h          |  2 --
 riscv/insns/vlwu.h         |  2 --
 riscv/insns/vmst.h         |  3 --
 riscv/insns/vmsv.h         |  4 ---
 riscv/insns/vmts.h         |  3 --
 riscv/insns/vmvv.h         |  4 ---
 riscv/insns/vsb.h          |  2 --
 riscv/insns/vsd.h          |  3 --
 riscv/insns/vsetvl.h       |  3 --
 riscv/insns/vsh.h          |  2 --
 riscv/insns/vssegb.h       |  0
 riscv/insns/vssegd.h       |  0
 riscv/insns/vssegh.h       |  0
 riscv/insns/vssegstb.h     |  0
 riscv/insns/vssegstd.h     |  0
 riscv/insns/vssegsth.h     |  0
 riscv/insns/vssegstw.h     |  0
 riscv/insns/vssegw.h       |  0
 riscv/insns/vsstb.h        |  2 --
 riscv/insns/vsstd.h        |  3 --
 riscv/insns/vssth.h        |  2 --
 riscv/insns/vsstw.h        |  2 --
 riscv/insns/vsw.h          |  2 --
 riscv/insns/vtcfg.h        |  5 ---
 riscv/insns/vtcfgivl.h     |  0
 riscv/insns/vvcfg.h        |  5 ---
 riscv/insns/vvcfgivl.h     |  6 ----
 riscv/insns/vxcptevac.h    |  0
 riscv/insns/vxcpthold.h    |  0
 riscv/insns/vxcptkill.h    |  0
 riscv/insns/vxcptrestore.h |  0
 riscv/insns/vxcptsave.h    |  0
 riscv/insns/vxcptwait.h    |  0
 riscv/opcodes.h            | 89 ----------------------------------------------
 riscv/processor.cc         |  8 -----
 93 files changed, 312 deletions(-)
 delete mode 100644 riscv/insns/fmovn.h
 delete mode 100644 riscv/insns/fmovz.h
 delete mode 100644 riscv/insns/movn.h
 delete mode 100644 riscv/insns/movz.h
 delete mode 100644 riscv/insns/stop.h
 delete mode 100644 riscv/insns/utidx.h
 delete mode 100644 riscv/insns/venqcmd.h
 delete mode 100644 riscv/insns/venqcnt.h
 delete mode 100644 riscv/insns/venqimm1.h
 delete mode 100644 riscv/insns/venqimm2.h
 delete mode 100644 riscv/insns/vf.h
 delete mode 100644 riscv/insns/vfld.h
 delete mode 100644 riscv/insns/vflsegd.h
 delete mode 100644 riscv/insns/vflsegstd.h
 delete mode 100644 riscv/insns/vflsegstw.h
 delete mode 100644 riscv/insns/vflsegw.h
 delete mode 100644 riscv/insns/vflstd.h
 delete mode 100644 riscv/insns/vflstw.h
 delete mode 100644 riscv/insns/vflw.h
 delete mode 100644 riscv/insns/vfmst.h
 delete mode 100644 riscv/insns/vfmsv.h
 delete mode 100644 riscv/insns/vfmts.h
 delete mode 100644 riscv/insns/vfmvv.h
 delete mode 100644 riscv/insns/vfsd.h
 delete mode 100644 riscv/insns/vfssegd.h
 delete mode 100644 riscv/insns/vfssegstd.h
 delete mode 100644 riscv/insns/vfssegstw.h
 delete mode 100644 riscv/insns/vfssegw.h
 delete mode 100644 riscv/insns/vfsstd.h
 delete mode 100644 riscv/insns/vfsstw.h
 delete mode 100644 riscv/insns/vfsw.h
 delete mode 100644 riscv/insns/vlb.h
 delete mode 100644 riscv/insns/vlbu.h
 delete mode 100644 riscv/insns/vld.h
 delete mode 100644 riscv/insns/vlh.h
 delete mode 100644 riscv/insns/vlhu.h
 delete mode 100644 riscv/insns/vlsegb.h
 delete mode 100644 riscv/insns/vlsegbu.h
 delete mode 100644 riscv/insns/vlsegd.h
 delete mode 100644 riscv/insns/vlsegh.h
 delete mode 100644 riscv/insns/vlseghu.h
 delete mode 100644 riscv/insns/vlsegstb.h
 delete mode 100644 riscv/insns/vlsegstbu.h
 delete mode 100644 riscv/insns/vlsegstd.h
 delete mode 100644 riscv/insns/vlsegsth.h
 delete mode 100644 riscv/insns/vlsegsthu.h
 delete mode 100644 riscv/insns/vlsegstw.h
 delete mode 100644 riscv/insns/vlsegstwu.h
 delete mode 100644 riscv/insns/vlsegw.h
 delete mode 100644 riscv/insns/vlsegwu.h
 delete mode 100644 riscv/insns/vlstb.h
 delete mode 100644 riscv/insns/vlstbu.h
 delete mode 100644 riscv/insns/vlstd.h
 delete mode 100644 riscv/insns/vlsth.h
 delete mode 100644 riscv/insns/vlsthu.h
 delete mode 100644 riscv/insns/vlstw.h
 delete mode 100644 riscv/insns/vlstwu.h
 delete mode 100644 riscv/insns/vlw.h
 delete mode 100644 riscv/insns/vlwu.h
 delete mode 100644 riscv/insns/vmst.h
 delete mode 100644 riscv/insns/vmsv.h
 delete mode 100644 riscv/insns/vmts.h
 delete mode 100644 riscv/insns/vmvv.h
 delete mode 100644 riscv/insns/vsb.h
 delete mode 100644 riscv/insns/vsd.h
 delete mode 100644 riscv/insns/vsetvl.h
 delete mode 100644 riscv/insns/vsh.h
 delete mode 100644 riscv/insns/vssegb.h
 delete mode 100644 riscv/insns/vssegd.h
 delete mode 100644 riscv/insns/vssegh.h
 delete mode 100644 riscv/insns/vssegstb.h
 delete mode 100644 riscv/insns/vssegstd.h
 delete mode 100644 riscv/insns/vssegsth.h
 delete mode 100644 riscv/insns/vssegstw.h
 delete mode 100644 riscv/insns/vssegw.h
 delete mode 100644 riscv/insns/vsstb.h
 delete mode 100644 riscv/insns/vsstd.h
 delete mode 100644 riscv/insns/vssth.h
 delete mode 100644 riscv/insns/vsstw.h
 delete mode 100644 riscv/insns/vsw.h
 delete mode 100644 riscv/insns/vtcfg.h
 delete mode 100644 riscv/insns/vtcfgivl.h
 delete mode 100644 riscv/insns/vvcfg.h
 delete mode 100644 riscv/insns/vvcfgivl.h
 delete mode 100644 riscv/insns/vxcptevac.h
 delete mode 100644 riscv/insns/vxcpthold.h
 delete mode 100644 riscv/insns/vxcptkill.h
 delete mode 100644 riscv/insns/vxcptrestore.h
 delete mode 100644 riscv/insns/vxcptsave.h
 delete mode 100644 riscv/insns/vxcptwait.h

(limited to 'riscv')

diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 57f43d7..86b70e0 100644
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -438,13 +438,6 @@ disassembler::disassembler()
   #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, frs1_reg)
   #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, frd_reg, xrs1_reg)
 
-  #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg)
-  #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg)
-  #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg)
-  #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg)
-  #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg)
-  #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg)
-
   DEFINE_XLOAD(lb)
   DEFINE_XLOAD(lbu)
   DEFINE_XLOAD(lh)
@@ -571,17 +564,6 @@ disassembler::disassembler()
   add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, xrd_reg, pcr_reg, imm));
   DEFINE_NOARG(eret)
 
-  DEFINE_RS1(vxcptsave);
-  DEFINE_RS1(vxcptrestore);
-  DEFINE_NOARG(vxcptkill);
-
-  DEFINE_RS1(vxcptevac);
-  DEFINE_NOARG(vxcpthold);
-  DEFINE_RS1_RS2(venqcmd);
-  DEFINE_RS1_RS2(venqimm1);
-  DEFINE_RS1_RS2(venqimm2);
-  DEFINE_RS1_RS2(venqcnt);
-
   DEFINE_FRTYPE(fadd_s);
   DEFINE_FRTYPE(fsub_s);
   DEFINE_FRTYPE(fmul_s);
@@ -646,58 +628,6 @@ disassembler::disassembler()
   add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr, xrd_reg, xrs1_reg));
   DEFINE_DTYPE(mffsr);
 
-  DEFINE_VEC_XMEM(vld);
-  DEFINE_VEC_XMEM(vlw);
-  DEFINE_VEC_XMEM(vlwu);
-  DEFINE_VEC_XMEM(vlh);
-  DEFINE_VEC_XMEM(vlhu);
-  DEFINE_VEC_XMEM(vlb);
-  DEFINE_VEC_XMEM(vlbu);
-  DEFINE_VEC_FMEM(vfld);
-  DEFINE_VEC_FMEM(vflw);
-  DEFINE_VEC_XMEMST(vlstd);
-  DEFINE_VEC_XMEMST(vlstw);
-  DEFINE_VEC_XMEMST(vlstwu);
-  DEFINE_VEC_XMEMST(vlsth);
-  DEFINE_VEC_XMEMST(vlsthu);
-  DEFINE_VEC_XMEMST(vlstb);
-  DEFINE_VEC_XMEMST(vlstbu);
-  DEFINE_VEC_FMEMST(vflstd);
-  DEFINE_VEC_FMEMST(vflstw);
-
-  DEFINE_VEC_XMEM(vsd);
-  DEFINE_VEC_XMEM(vsw);
-  DEFINE_VEC_XMEM(vsh);
-  DEFINE_VEC_XMEM(vsb);
-  DEFINE_VEC_FMEM(vfsd);
-  DEFINE_VEC_FMEM(vfsw);
-  DEFINE_VEC_XMEMST(vsstd);
-  DEFINE_VEC_XMEMST(vsstw);
-  DEFINE_VEC_XMEMST(vssth);
-  DEFINE_VEC_XMEMST(vsstb);
-  DEFINE_VEC_FMEMST(vfsstd);
-  DEFINE_VEC_FMEMST(vfsstw);
-
-  DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg);
-  DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg);
-  DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg);
-  DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg);
-  DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg);
-  DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg);
-  DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg);
-  DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg);
-
-  DEFINE_RS1_RS2(vvcfg);
-  DEFINE_RS1_RS2(vtcfg);
-
-  DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
-  DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
-  DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg);
-  DISASM_INSN("vf", vf, 0, xrs1_reg, imm);
-
-  DEFINE_NOARG(fence_v_l);
-  DEFINE_NOARG(fence_v_g);
-
   // provide a default disassembly for all instructions as a fallback
   #define DECLARE_INSN(code, match, mask) \
    add_insn(new disasm_insn_t(#code " (args unknown)", match, mask));
diff --git a/riscv/insns/fmovn.h b/riscv/insns/fmovn.h
deleted file mode 100644
index 394b56c..0000000
--- a/riscv/insns/fmovn.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-if (RS1 & 0x1) FRD = FRS2;
diff --git a/riscv/insns/fmovz.h b/riscv/insns/fmovz.h
deleted file mode 100644
index 7862216..0000000
--- a/riscv/insns/fmovz.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-if (~RS1 & 0x1) FRD = FRS2;
diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h
deleted file mode 100644
index 402d6d3..0000000
--- a/riscv/insns/movn.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-if (RS1 & 0x1) RD = RS2;
diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h
deleted file mode 100644
index 74cf8a9..0000000
--- a/riscv/insns/movz.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-if (~RS1 & 0x1) RD = RS2;
diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h
deleted file mode 100644
index 791a82c..0000000
--- a/riscv/insns/stop.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-utmode = false;
-throw vt_command_stop;
diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h
deleted file mode 100644
index b3c944c..0000000
--- a/riscv/insns/utidx.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-RD = utidx;
diff --git a/riscv/insns/venqcmd.h b/riscv/insns/venqcmd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/venqcnt.h b/riscv/insns/venqcnt.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/venqimm1.h b/riscv/insns/venqimm1.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/venqimm2.h b/riscv/insns/venqimm2.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
deleted file mode 100644
index 162cbe6..0000000
--- a/riscv/insns/vf.h
+++ /dev/null
@@ -1,9 +0,0 @@
-require_vector;
-for (int i=0; i<VL; i++)
-{
-  uts[i]->pc = ITYPE_EADDR;
-  uts[i]->utmode = true;
-  uts[i]->run = true;
-  while (uts[i]->utmode)
-    uts[i]->step(100, false); // XXX
-}
diff --git a/riscv/insns/vfld.h b/riscv/insns/vfld.h
deleted file mode 100644
index 9b40470..0000000
--- a/riscv/insns/vfld.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, 8);
diff --git a/riscv/insns/vflsegd.h b/riscv/insns/vflsegd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vflsegstd.h b/riscv/insns/vflsegstd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vflsegstw.h b/riscv/insns/vflsegstw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vflsegw.h b/riscv/insns/vflsegw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vflstd.h b/riscv/insns/vflstd.h
deleted file mode 100644
index fa9b32d..0000000
--- a/riscv/insns/vflstd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, RS2);
diff --git a/riscv/insns/vflstw.h b/riscv/insns/vflstw.h
deleted file mode 100644
index 716c818..0000000
--- a/riscv/insns/vflstw.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, RS2);
diff --git a/riscv/insns/vflw.h b/riscv/insns/vflw.h
deleted file mode 100644
index 75fdd04..0000000
--- a/riscv/insns/vflw.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, 4);
diff --git a/riscv/insns/vfmst.h b/riscv/insns/vfmst.h
deleted file mode 100644
index 686d7c5..0000000
--- a/riscv/insns/vfmst.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_FRD(RS2) = FRS1;
diff --git a/riscv/insns/vfmsv.h b/riscv/insns/vfmsv.h
deleted file mode 100644
index a9aa876..0000000
--- a/riscv/insns/vfmsv.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = FRS1;
-UT_LOOP_END
diff --git a/riscv/insns/vfmts.h b/riscv/insns/vfmts.h
deleted file mode 100644
index a6da126..0000000
--- a/riscv/insns/vfmts.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-FRD = UT_FRS1(RS2);
diff --git a/riscv/insns/vfmvv.h b/riscv/insns/vfmvv.h
deleted file mode 100644
index 279da21..0000000
--- a/riscv/insns/vfmvv.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = UT_LOOP_FRS1;
-UT_LOOP_END
diff --git a/riscv/insns/vfsd.h b/riscv/insns/vfsd.h
deleted file mode 100644
index f619fc8..0000000
--- a/riscv/insns/vfsd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, 8);
diff --git a/riscv/insns/vfssegd.h b/riscv/insns/vfssegd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vfssegstd.h b/riscv/insns/vfssegstd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vfssegstw.h b/riscv/insns/vfssegstw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vfssegw.h b/riscv/insns/vfssegw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vfsstd.h b/riscv/insns/vfsstd.h
deleted file mode 100644
index b3bb260..0000000
--- a/riscv/insns/vfsstd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, RS2);
diff --git a/riscv/insns/vfsstw.h b/riscv/insns/vfsstw.h
deleted file mode 100644
index 9cef9b0..0000000
--- a/riscv/insns/vfsstw.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, RS2);
diff --git a/riscv/insns/vfsw.h b/riscv/insns/vfsw.h
deleted file mode 100644
index 3fe3d3f..0000000
--- a/riscv/insns/vfsw.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, 4);
diff --git a/riscv/insns/vlb.h b/riscv/insns/vlb.h
deleted file mode 100644
index 618380a..0000000
--- a/riscv/insns/vlb.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, 1);
diff --git a/riscv/insns/vlbu.h b/riscv/insns/vlbu.h
deleted file mode 100644
index f92c8b5..0000000
--- a/riscv/insns/vlbu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, 1);
diff --git a/riscv/insns/vld.h b/riscv/insns/vld.h
deleted file mode 100644
index fb7a3c5..0000000
--- a/riscv/insns/vld.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, 8);
diff --git a/riscv/insns/vlh.h b/riscv/insns/vlh.h
deleted file mode 100644
index 269c2a8..0000000
--- a/riscv/insns/vlh.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, 2);
diff --git a/riscv/insns/vlhu.h b/riscv/insns/vlhu.h
deleted file mode 100644
index 7a2019d..0000000
--- a/riscv/insns/vlhu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, 2);
diff --git a/riscv/insns/vlsegb.h b/riscv/insns/vlsegb.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegbu.h b/riscv/insns/vlsegbu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegd.h b/riscv/insns/vlsegd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegh.h b/riscv/insns/vlsegh.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlseghu.h b/riscv/insns/vlseghu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegstb.h b/riscv/insns/vlsegstb.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegstbu.h b/riscv/insns/vlsegstbu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegstd.h b/riscv/insns/vlsegstd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegsth.h b/riscv/insns/vlsegsth.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegsthu.h b/riscv/insns/vlsegsthu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegstw.h b/riscv/insns/vlsegstw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegstwu.h b/riscv/insns/vlsegstwu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegw.h b/riscv/insns/vlsegw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlsegwu.h b/riscv/insns/vlsegwu.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vlstb.h b/riscv/insns/vlstb.h
deleted file mode 100644
index 219d90e..0000000
--- a/riscv/insns/vlstb.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, RS2);
diff --git a/riscv/insns/vlstbu.h b/riscv/insns/vlstbu.h
deleted file mode 100644
index 09faa29..0000000
--- a/riscv/insns/vlstbu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, RS2);
diff --git a/riscv/insns/vlstd.h b/riscv/insns/vlstd.h
deleted file mode 100644
index 5e5de9c..0000000
--- a/riscv/insns/vlstd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, RS2);
diff --git a/riscv/insns/vlsth.h b/riscv/insns/vlsth.h
deleted file mode 100644
index af6b5b5..0000000
--- a/riscv/insns/vlsth.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, RS2);
diff --git a/riscv/insns/vlsthu.h b/riscv/insns/vlsthu.h
deleted file mode 100644
index 0fe8452..0000000
--- a/riscv/insns/vlsthu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, RS2);
diff --git a/riscv/insns/vlstw.h b/riscv/insns/vlstw.h
deleted file mode 100644
index 5375dc0..0000000
--- a/riscv/insns/vlstw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, RS2);
diff --git a/riscv/insns/vlstwu.h b/riscv/insns/vlstwu.h
deleted file mode 100644
index 328e23f..0000000
--- a/riscv/insns/vlstwu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, RS2);
diff --git a/riscv/insns/vlw.h b/riscv/insns/vlw.h
deleted file mode 100644
index 6e35911..0000000
--- a/riscv/insns/vlw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, 4);
diff --git a/riscv/insns/vlwu.h b/riscv/insns/vlwu.h
deleted file mode 100644
index 4fa1489..0000000
--- a/riscv/insns/vlwu.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, 4);
diff --git a/riscv/insns/vmst.h b/riscv/insns/vmst.h
deleted file mode 100644
index f4d03d9..0000000
--- a/riscv/insns/vmst.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-UT_RD(RS2) = RS1;
diff --git a/riscv/insns/vmsv.h b/riscv/insns/vmsv.h
deleted file mode 100644
index c6f4c2c..0000000
--- a/riscv/insns/vmsv.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = RS1;
-UT_LOOP_END
diff --git a/riscv/insns/vmts.h b/riscv/insns/vmts.h
deleted file mode 100644
index 2d463bc..0000000
--- a/riscv/insns/vmts.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-assert(0 <= RS2 && RS2 < MAX_UTS);
-RD = UT_RS1(RS2);
diff --git a/riscv/insns/vmvv.h b/riscv/insns/vmvv.h
deleted file mode 100644
index 91d63d4..0000000
--- a/riscv/insns/vmvv.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = UT_LOOP_RS1;
-UT_LOOP_END
diff --git a/riscv/insns/vsb.h b/riscv/insns/vsb.h
deleted file mode 100644
index c3d5b9d..0000000
--- a/riscv/insns/vsb.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, 1);
diff --git a/riscv/insns/vsd.h b/riscv/insns/vsd.h
deleted file mode 100644
index 9c02069..0000000
--- a/riscv/insns/vsd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, 8);
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h
deleted file mode 100644
index c2212ff..0000000
--- a/riscv/insns/vsetvl.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-setvl(RS1);
-RD = VL;
diff --git a/riscv/insns/vsh.h b/riscv/insns/vsh.h
deleted file mode 100644
index 623eda8..0000000
--- a/riscv/insns/vsh.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, 2);
diff --git a/riscv/insns/vssegb.h b/riscv/insns/vssegb.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegd.h b/riscv/insns/vssegd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegh.h b/riscv/insns/vssegh.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegstb.h b/riscv/insns/vssegstb.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vsstb.h b/riscv/insns/vsstb.h
deleted file mode 100644
index b83cc50..0000000
--- a/riscv/insns/vsstb.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, RS2);
diff --git a/riscv/insns/vsstd.h b/riscv/insns/vsstd.h
deleted file mode 100644
index 26868d2..0000000
--- a/riscv/insns/vsstd.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, RS2);
diff --git a/riscv/insns/vssth.h b/riscv/insns/vssth.h
deleted file mode 100644
index 3904331..0000000
--- a/riscv/insns/vssth.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, RS2);
diff --git a/riscv/insns/vsstw.h b/riscv/insns/vsstw.h
deleted file mode 100644
index 8f05953..0000000
--- a/riscv/insns/vsstw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, RS2);
diff --git a/riscv/insns/vsw.h b/riscv/insns/vsw.h
deleted file mode 100644
index 662d4e3..0000000
--- a/riscv/insns/vsw.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, 4);
diff --git a/riscv/insns/vtcfg.h b/riscv/insns/vtcfg.h
deleted file mode 100644
index 6e8cbd1..0000000
--- a/riscv/insns/vtcfg.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);
diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vvcfg.h b/riscv/insns/vvcfg.h
deleted file mode 100644
index 6e8cbd1..0000000
--- a/riscv/insns/vvcfg.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-nxpr_use = RS1 & 0x3f;
-nfpr_use = RS2 & 0x3f;
-vcfg();
-setvl(0);
diff --git a/riscv/insns/vvcfgivl.h b/riscv/insns/vvcfgivl.h
deleted file mode 100644
index 0ded9f8..0000000
--- a/riscv/insns/vvcfgivl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-require_vector;
-nxpr_use = SIMM & 0x3f;
-nfpr_use = (SIMM >> 6) & 0x3f;
-vcfg();
-setvl(RS1);
-RD = VL;
diff --git a/riscv/insns/vxcptevac.h b/riscv/insns/vxcptevac.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vxcpthold.h b/riscv/insns/vxcpthold.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vxcptkill.h b/riscv/insns/vxcptkill.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vxcptrestore.h b/riscv/insns/vxcptrestore.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vxcptsave.h b/riscv/insns/vxcptsave.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/insns/vxcptwait.h b/riscv/insns/vxcptwait.h
deleted file mode 100644
index e69de29..0000000
diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index f18aebd..34e10c1 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -1,17 +1,10 @@
-DECLARE_INSN(movn, 0x6f7, 0x1ffff)
-DECLARE_INSN(vfsstw, 0x150f, 0x1ffff)
 DECLARE_INSN(remuw, 0x7bb, 0x1ffff)
 DECLARE_INSN(fmin_d, 0x180d3, 0x1ffff)
 DECLARE_INSN(lr_w, 0x1012b, 0x3fffff)
-DECLARE_INSN(vlsthu, 0x128b, 0x1ffff)
 DECLARE_INSN(bltu, 0x363, 0x3ff)
-DECLARE_INSN(vlsegstwu, 0xb0b, 0xfff)
-DECLARE_INSN(vvcfg, 0x473, 0xf801ffff)
-DECLARE_INSN(movz, 0x2f7, 0x1ffff)
 DECLARE_INSN(fmin_s, 0x18053, 0x1ffff)
 DECLARE_INSN(slliw, 0x9b, 0x3f83ff)
 DECLARE_INSN(lb, 0x3, 0x3ff)
-DECLARE_INSN(vlwu, 0x30b, 0x3fffff)
 DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff)
 DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff)
 DECLARE_INSN(lh, 0x83, 0x3ff)
@@ -24,53 +17,32 @@ DECLARE_INSN(fmax_d, 0x190d3, 0x1ffff)
 DECLARE_INSN(bne, 0xe3, 0x3ff)
 DECLARE_INSN(rdcycle, 0x277, 0x7ffffff)
 DECLARE_INSN(fcvt_s_d, 0x11053, 0x3ff1ff)
-DECLARE_INSN(vlh, 0x8b, 0x3fffff)
 DECLARE_INSN(bgeu, 0x3e3, 0x3ff)
-DECLARE_INSN(vflstd, 0x158b, 0x1ffff)
 DECLARE_INSN(fadd_d, 0xd3, 0x1f1ff)
 DECLARE_INSN(sltiu, 0x193, 0x3ff)
 DECLARE_INSN(mtpcr, 0x1fb, 0x1ffff)
-DECLARE_INSN(vlb, 0xb, 0x3fffff)
-DECLARE_INSN(stop, 0x177, 0xffffffff)
-DECLARE_INSN(vld, 0x18b, 0x3fffff)
 DECLARE_INSN(break, 0xf7, 0xffffffff)
 DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff)
-DECLARE_INSN(vflstw, 0x150b, 0x1ffff)
 DECLARE_INSN(mul, 0x433, 0x1ffff)
-DECLARE_INSN(vxcptevac, 0x237b, 0xf83fffff)
-DECLARE_INSN(vlw, 0x10b, 0x3fffff)
-DECLARE_INSN(vssegstw, 0x90f, 0xfff)
 DECLARE_INSN(amominu_d, 0x19ab, 0x1ffff)
 DECLARE_INSN(mftx_d, 0x1c0d3, 0x3fffff)
 DECLARE_INSN(srli, 0x293, 0x3f03ff)
 DECLARE_INSN(amominu_w, 0x192b, 0x1ffff)
 DECLARE_INSN(divuw, 0x6bb, 0x1ffff)
 DECLARE_INSN(mulw, 0x43b, 0x1ffff)
-DECLARE_INSN(vssegstd, 0x98f, 0xfff)
 DECLARE_INSN(srlw, 0x2bb, 0x1ffff)
-DECLARE_INSN(vssegstb, 0x80f, 0xfff)
-DECLARE_INSN(utidx, 0x1f7, 0x7ffffff)
 DECLARE_INSN(div, 0x633, 0x1ffff)
-DECLARE_INSN(vtcfg, 0xc73, 0xf801ffff)
 DECLARE_INSN(mftx_s, 0x1c053, 0x3fffff)
-DECLARE_INSN(vssegsth, 0x88f, 0xfff)
-DECLARE_INSN(vvcfgivl, 0xf3, 0x3ff)
 DECLARE_INSN(j, 0x67, 0x7f)
 DECLARE_INSN(fence, 0x12f, 0x3ff)
-DECLARE_INSN(vsw, 0x10f, 0x3fffff)
 DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff)
-DECLARE_INSN(vfssegstd, 0xd8f, 0xfff)
 DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff)
 DECLARE_INSN(fle_s, 0x17053, 0x1ffff)
 DECLARE_INSN(fence_v_l, 0x22f, 0x3ff)
-DECLARE_INSN(vsb, 0xf, 0x3fffff)
 DECLARE_INSN(mffsr, 0x1d053, 0x7ffffff)
 DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff)
-DECLARE_INSN(vlstbu, 0x120b, 0x1ffff)
-DECLARE_INSN(vsetvl, 0x2f3, 0x3fffff)
 DECLARE_INSN(fle_d, 0x170d3, 0x1ffff)
 DECLARE_INSN(fence_i, 0xaf, 0x3ff)
-DECLARE_INSN(vlsegbu, 0x220b, 0x1ffff)
 DECLARE_INSN(fnmsub_d, 0xcb, 0x1ff)
 DECLARE_INSN(addw, 0x3b, 0x1ffff)
 DECLARE_INSN(sll, 0xb3, 0x1ffff)
@@ -78,21 +50,15 @@ DECLARE_INSN(xor, 0x233, 0x1ffff)
 DECLARE_INSN(sub, 0x10033, 0x1ffff)
 DECLARE_INSN(eret, 0x27b, 0xffffffff)
 DECLARE_INSN(blt, 0x263, 0x3ff)
-DECLARE_INSN(vsstw, 0x110f, 0x1ffff)
 DECLARE_INSN(mtfsr, 0x1f053, 0x3fffff)
-DECLARE_INSN(vssth, 0x108f, 0x1ffff)
 DECLARE_INSN(sc_w, 0x1052b, 0x1ffff)
 DECLARE_INSN(rem, 0x733, 0x1ffff)
 DECLARE_INSN(srliw, 0x29b, 0x3f83ff)
 DECLARE_INSN(lui, 0x37, 0x7f)
-DECLARE_INSN(vsstb, 0x100f, 0x1ffff)
 DECLARE_INSN(fcvt_s_lu, 0xd053, 0x3ff1ff)
-DECLARE_INSN(vsstd, 0x118f, 0x1ffff)
 DECLARE_INSN(addi, 0x13, 0x3ff)
-DECLARE_INSN(vfmst, 0x1173, 0x1ffff)
 DECLARE_INSN(mulh, 0x4b3, 0x1ffff)
 DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff)
-DECLARE_INSN(vlsegsthu, 0xa8b, 0xfff)
 DECLARE_INSN(srai, 0x10293, 0x3f03ff)
 DECLARE_INSN(amoand_d, 0x9ab, 0x1ffff)
 DECLARE_INSN(flt_d, 0x160d3, 0x1ffff)
@@ -107,45 +73,29 @@ DECLARE_INSN(feq_s, 0x15053, 0x1ffff)
 DECLARE_INSN(fsgnjx_d, 0x70d3, 0x1ffff)
 DECLARE_INSN(sra, 0x102b3, 0x1ffff)
 DECLARE_INSN(bge, 0x2e3, 0x3ff)
-DECLARE_INSN(venqimm2, 0x337b, 0xf801ffff)
 DECLARE_INSN(sraiw, 0x1029b, 0x3f83ff)
-DECLARE_INSN(vssegd, 0x218f, 0x1ffff)
 DECLARE_INSN(srl, 0x2b3, 0x1ffff)
-DECLARE_INSN(venqcmd, 0x2b7b, 0xf801ffff)
 DECLARE_INSN(fsub_d, 0x10d3, 0x1f1ff)
-DECLARE_INSN(vfmts, 0x1973, 0x1ffff)
-DECLARE_INSN(venqimm1, 0x2f7b, 0xf801ffff)
 DECLARE_INSN(fsgnjx_s, 0x7053, 0x1ffff)
-DECLARE_INSN(vfmsv, 0x973, 0x3fffff)
 DECLARE_INSN(feq_d, 0x150d3, 0x1ffff)
 DECLARE_INSN(fcvt_d_wu, 0xf0d3, 0x3ff1ff)
-DECLARE_INSN(vxcptrestore, 0x77b, 0xf83fffff)
-DECLARE_INSN(vmts, 0x1873, 0x1ffff)
 DECLARE_INSN(or, 0x333, 0x1ffff)
 DECLARE_INSN(rdinstret, 0xa77, 0x7ffffff)
 DECLARE_INSN(fcvt_wu_d, 0xb0d3, 0x3ff1ff)
 DECLARE_INSN(subw, 0x1003b, 0x1ffff)
 DECLARE_INSN(fmax_s, 0x19053, 0x1ffff)
 DECLARE_INSN(amomaxu_d, 0x1dab, 0x1ffff)
-DECLARE_INSN(vlstw, 0x110b, 0x1ffff)
-DECLARE_INSN(vlsth, 0x108b, 0x1ffff)
 DECLARE_INSN(xori, 0x213, 0x3ff)
 DECLARE_INSN(fdiv_d, 0x30d3, 0x1f1ff)
 DECLARE_INSN(amomaxu_w, 0x1d2b, 0x1ffff)
 DECLARE_INSN(fcvt_wu_s, 0xb053, 0x3ff1ff)
-DECLARE_INSN(vlstb, 0x100b, 0x1ffff)
-DECLARE_INSN(vlstd, 0x118b, 0x1ffff)
 DECLARE_INSN(rdtime, 0x677, 0x7ffffff)
 DECLARE_INSN(andi, 0x393, 0x3ff)
 DECLARE_INSN(clearpcr, 0x7b, 0x3ff)
-DECLARE_INSN(venqcnt, 0x377b, 0xf801ffff)
 DECLARE_INSN(fsgnjn_d, 0x60d3, 0x1ffff)
 DECLARE_INSN(fnmadd_s, 0x4f, 0x1ff)
 DECLARE_INSN(jal, 0x6f, 0x7f)
 DECLARE_INSN(lwu, 0x303, 0x3ff)
-DECLARE_INSN(vlsegstbu, 0xa0b, 0xfff)
-DECLARE_INSN(vlhu, 0x28b, 0x3fffff)
-DECLARE_INSN(vfsstd, 0x158f, 0x1ffff)
 DECLARE_INSN(fnmadd_d, 0xcf, 0x1ff)
 DECLARE_INSN(amoadd_d, 0x1ab, 0x1ffff)
 DECLARE_INSN(lr_d, 0x101ab, 0x3fffff)
@@ -156,9 +106,6 @@ DECLARE_INSN(fcvt_d_lu, 0xd0d3, 0x3ff1ff)
 DECLARE_INSN(amomax_d, 0x15ab, 0x1ffff)
 DECLARE_INSN(fsd, 0x1a7, 0x3ff)
 DECLARE_INSN(fcvt_w_d, 0xa0d3, 0x3ff1ff)
-DECLARE_INSN(fmovz, 0xaf7, 0x1ffff)
-DECLARE_INSN(vmvv, 0x73, 0x3fffff)
-DECLARE_INSN(vfssegstw, 0xd0f, 0xfff)
 DECLARE_INSN(slt, 0x133, 0x1ffff)
 DECLARE_INSN(mxtf_d, 0x1e0d3, 0x3fffff)
 DECLARE_INSN(sllw, 0xbb, 0x1ffff)
@@ -169,80 +116,44 @@ DECLARE_INSN(flw, 0x107, 0x3ff)
 DECLARE_INSN(remw, 0x73b, 0x1ffff)
 DECLARE_INSN(sltu, 0x1b3, 0x1ffff)
 DECLARE_INSN(slli, 0x93, 0x3f03ff)
-DECLARE_INSN(vssegw, 0x210f, 0x1ffff)
 DECLARE_INSN(amoor_w, 0xd2b, 0x1ffff)
-DECLARE_INSN(vsd, 0x18f, 0x3fffff)
 DECLARE_INSN(beq, 0x63, 0x3ff)
 DECLARE_INSN(fld, 0x187, 0x3ff)
 DECLARE_INSN(mxtf_s, 0x1e053, 0x3fffff)
 DECLARE_INSN(fsub_s, 0x1053, 0x1f1ff)
 DECLARE_INSN(and, 0x3b3, 0x1ffff)
-DECLARE_INSN(vtcfgivl, 0x1f3, 0x3ff)
 DECLARE_INSN(lbu, 0x203, 0x3ff)
-DECLARE_INSN(vf, 0x3f3, 0xf80003ff)
-DECLARE_INSN(vlsegstw, 0x90b, 0xfff)
 DECLARE_INSN(syscall, 0x77, 0xffffffff)
 DECLARE_INSN(fsgnj_s, 0x5053, 0x1ffff)
-DECLARE_INSN(vfmvv, 0x173, 0x3fffff)
-DECLARE_INSN(vlstwu, 0x130b, 0x1ffff)
-DECLARE_INSN(vsh, 0x8f, 0x3fffff)
-DECLARE_INSN(vlsegstb, 0x80b, 0xfff)
-DECLARE_INSN(vxcptsave, 0x37b, 0xf83fffff)
-DECLARE_INSN(vlsegstd, 0x98b, 0xfff)
-DECLARE_INSN(vflsegd, 0x258b, 0x1ffff)
-DECLARE_INSN(vflsegw, 0x250b, 0x1ffff)
-DECLARE_INSN(vlsegsth, 0x88b, 0xfff)
 DECLARE_INSN(amomax_w, 0x152b, 0x1ffff)
 DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff)
-DECLARE_INSN(vflsegstw, 0xd0b, 0xfff)
 DECLARE_INSN(mulhu, 0x5b3, 0x1ffff)
 DECLARE_INSN(fence_v_g, 0x2af, 0x3ff)
-DECLARE_INSN(vmsv, 0x873, 0x3fffff)
-DECLARE_INSN(vmst, 0x1073, 0x1ffff)
 DECLARE_INSN(setpcr, 0xfb, 0x3ff)
 DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff)
-DECLARE_INSN(vxcpthold, 0x277b, 0xffffffff)
 DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff)
-DECLARE_INSN(vflsegstd, 0xd8b, 0xfff)
 DECLARE_INSN(auipc, 0x17, 0x7f)
 DECLARE_INSN(fcvt_lu_d, 0x90d3, 0x3ff1ff)
-DECLARE_INSN(vfld, 0x58b, 0x3fffff)
 DECLARE_INSN(sc_d, 0x105ab, 0x1ffff)
 DECLARE_INSN(fmadd_s, 0x43, 0x1ff)
-DECLARE_INSN(fmovn, 0xef7, 0x1ffff)
-DECLARE_INSN(vssegh, 0x208f, 0x1ffff)
 DECLARE_INSN(fsqrt_s, 0x4053, 0x3ff1ff)
-DECLARE_INSN(vxcptkill, 0xb7b, 0xffffffff)
 DECLARE_INSN(amomin_w, 0x112b, 0x1ffff)
 DECLARE_INSN(fsgnjn_s, 0x6053, 0x1ffff)
-DECLARE_INSN(vlsegwu, 0x230b, 0x1ffff)
-DECLARE_INSN(vfsw, 0x50f, 0x3fffff)
 DECLARE_INSN(amoswap_d, 0x5ab, 0x1ffff)
 DECLARE_INSN(fsqrt_d, 0x40d3, 0x3ff1ff)
-DECLARE_INSN(vflw, 0x50b, 0x3fffff)
 DECLARE_INSN(fmadd_d, 0xc3, 0x1ff)
 DECLARE_INSN(divw, 0x63b, 0x1ffff)
 DECLARE_INSN(amomin_d, 0x11ab, 0x1ffff)
 DECLARE_INSN(divu, 0x6b3, 0x1ffff)
 DECLARE_INSN(amoswap_w, 0x52b, 0x1ffff)
-DECLARE_INSN(vfsd, 0x58f, 0x3fffff)
 DECLARE_INSN(jalr, 0x6b, 0x3ff)
 DECLARE_INSN(fadd_s, 0x53, 0x1f1ff)
-DECLARE_INSN(vlsegb, 0x200b, 0x1ffff)
 DECLARE_INSN(fcvt_l_d, 0x80d3, 0x3ff1ff)
-DECLARE_INSN(vlsegd, 0x218b, 0x1ffff)
-DECLARE_INSN(vlsegh, 0x208b, 0x1ffff)
 DECLARE_INSN(sw, 0x123, 0x3ff)
 DECLARE_INSN(fmsub_s, 0x47, 0x1ff)
-DECLARE_INSN(vfssegw, 0x250f, 0x1ffff)
 DECLARE_INSN(lhu, 0x283, 0x3ff)
 DECLARE_INSN(sh, 0xa3, 0x3ff)
-DECLARE_INSN(vlsegw, 0x210b, 0x1ffff)
 DECLARE_INSN(fsw, 0x127, 0x3ff)
-DECLARE_INSN(vlbu, 0x20b, 0x3fffff)
 DECLARE_INSN(sb, 0x23, 0x3ff)
 DECLARE_INSN(fmsub_d, 0xc7, 0x1ff)
-DECLARE_INSN(vlseghu, 0x228b, 0x1ffff)
-DECLARE_INSN(vssegb, 0x200f, 0x1ffff)
-DECLARE_INSN(vfssegd, 0x258f, 0x1ffff)
 DECLARE_INSN(sd, 0x1a3, 0x3ff)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3bd4a19..42182bd 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -261,10 +261,6 @@ void processor_t::set_pcr(int which, reg_t val)
     case PCR_K1:
       pcr_k1 = val;
       break;
-    case PCR_VECBANK:
-      vecbanks = val & 0xff;
-      vecbanks_count = __builtin_popcountll(vecbanks);
-      break;
     case PCR_TOHOST:
       if (tohost == 0)
         tohost = val;
@@ -304,10 +300,6 @@ reg_t processor_t::get_pcr(int which)
       return pcr_k0;
     case PCR_K1:
       return pcr_k1;
-    case PCR_VECBANK:
-      return vecbanks;
-    case PCR_VECCFG:
-      return nfpr_use << 18 | nxpr_use << 12 | vl;
     case PCR_TOHOST:
       return tohost;
     case PCR_FROMHOST:
-- 
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