From 7471eee0ba7d80c83048cbbf47d7837f586b9264 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Fri, 5 Nov 2010 14:06:12 -0700
Subject: [xcc, sim, pk, opcodes] new instruction encoding!

---
 riscv/decode.h            |  43 +--
 riscv/execute.h           | 656 +++++++++++++++++++++++-----------------------
 riscv/insns/add.h         |   2 +-
 riscv/insns/add_d.h       |   2 +-
 riscv/insns/add_d_rm.h    |   2 +-
 riscv/insns/add_s.h       |   2 +-
 riscv/insns/add_s_rm.h    |   2 +-
 riscv/insns/addi.h        |   2 +-
 riscv/insns/addiw.h       |   2 +-
 riscv/insns/addw.h        |   2 +-
 riscv/insns/amo_add.h     |   2 +-
 riscv/insns/amo_and.h     |   2 +-
 riscv/insns/amo_max.h     |   2 +-
 riscv/insns/amo_maxu.h    |   2 +-
 riscv/insns/amo_min.h     |   2 +-
 riscv/insns/amo_minu.h    |   2 +-
 riscv/insns/amo_or.h      |   2 +-
 riscv/insns/amo_swap.h    |   2 +-
 riscv/insns/amow_add.h    |   2 +-
 riscv/insns/amow_and.h    |   2 +-
 riscv/insns/amow_max.h    |   2 +-
 riscv/insns/amow_maxu.h   |   2 +-
 riscv/insns/amow_min.h    |   2 +-
 riscv/insns/amow_minu.h   |   2 +-
 riscv/insns/amow_or.h     |   2 +-
 riscv/insns/amow_swap.h   |   2 +-
 riscv/insns/and.h         |   2 +-
 riscv/insns/andi.h        |   2 +-
 riscv/insns/break.h       |   1 -
 riscv/insns/c_eq_d.h      |   2 +-
 riscv/insns/c_eq_s.h      |   2 +-
 riscv/insns/c_le_d.h      |   2 +-
 riscv/insns/c_le_s.h      |   2 +-
 riscv/insns/c_lt_d.h      |   2 +-
 riscv/insns/c_lt_s.h      |   2 +-
 riscv/insns/cvt_d_l.h     |   2 +-
 riscv/insns/cvt_d_l_rm.h  |   2 +-
 riscv/insns/cvt_d_s.h     |   2 +-
 riscv/insns/cvt_d_s_rm.h  |   2 +-
 riscv/insns/cvt_d_w.h     |   2 +-
 riscv/insns/cvt_d_w_rm.h  |   2 +-
 riscv/insns/cvt_l_d_rm.h  |   2 +-
 riscv/insns/cvt_l_s_rm.h  |   2 +-
 riscv/insns/cvt_s_d.h     |   2 +-
 riscv/insns/cvt_s_d_rm.h  |   2 +-
 riscv/insns/cvt_s_l.h     |   2 +-
 riscv/insns/cvt_s_l_rm.h  |   2 +-
 riscv/insns/cvt_s_w.h     |   2 +-
 riscv/insns/cvt_s_w_rm.h  |   2 +-
 riscv/insns/cvt_w_d_rm.h  |   2 +-
 riscv/insns/cvt_w_s_rm.h  |   2 +-
 riscv/insns/cvtu_d_l.h    |   2 +-
 riscv/insns/cvtu_d_l_rm.h |   2 +-
 riscv/insns/cvtu_d_w.h    |   2 +-
 riscv/insns/cvtu_d_w_rm.h |   2 +-
 riscv/insns/cvtu_l_d_rm.h |   2 +-
 riscv/insns/cvtu_l_s_rm.h |   2 +-
 riscv/insns/cvtu_s_l.h    |   2 +-
 riscv/insns/cvtu_s_l_rm.h |   2 +-
 riscv/insns/cvtu_s_w.h    |   2 +-
 riscv/insns/cvtu_s_w_rm.h |   2 +-
 riscv/insns/cvtu_w_d_rm.h |   2 +-
 riscv/insns/cvtu_w_s_rm.h |   2 +-
 riscv/insns/di.h          |   2 +-
 riscv/insns/div.h         |   2 +-
 riscv/insns/div_d.h       |   2 +-
 riscv/insns/div_d_rm.h    |   2 +-
 riscv/insns/div_s.h       |   2 +-
 riscv/insns/div_s_rm.h    |   2 +-
 riscv/insns/divu.h        |   2 +-
 riscv/insns/divuw.h       |   2 +-
 riscv/insns/divw.h        |   2 +-
 riscv/insns/ei.h          |   2 +-
 riscv/insns/jalr_c.h      |   4 +-
 riscv/insns/l_d.h         |   2 +-
 riscv/insns/l_s.h         |   2 +-
 riscv/insns/lb.h          |   2 +-
 riscv/insns/lbu.h         |   2 +-
 riscv/insns/ld.h          |   2 +-
 riscv/insns/lh.h          |   2 +-
 riscv/insns/lhu.h         |   2 +-
 riscv/insns/lui.h         |   2 +-
 riscv/insns/lw.h          |   2 +-
 riscv/insns/lwu.h         |   2 +-
 riscv/insns/madd_d.h      |   2 +-
 riscv/insns/madd_d_rm.h   |   2 +-
 riscv/insns/madd_s.h      |   2 +-
 riscv/insns/madd_s_rm.h   |   2 +-
 riscv/insns/mfcr.h        |   2 +-
 riscv/insns/mff_d.h       |   2 +-
 riscv/insns/mff_s.h       |   2 +-
 riscv/insns/mffh_d.h      |   2 +-
 riscv/insns/mffl_d.h      |   2 +-
 riscv/insns/mfpcr.h       |   2 +-
 riscv/insns/msub_d.h      |   2 +-
 riscv/insns/msub_d_rm.h   |   2 +-
 riscv/insns/msub_s.h      |   2 +-
 riscv/insns/msub_s_rm.h   |   2 +-
 riscv/insns/mtf_d.h       |   2 +-
 riscv/insns/mtf_s.h       |   2 +-
 riscv/insns/mtflh_d.h     |   2 +-
 riscv/insns/mul.h         |   2 +-
 riscv/insns/mul_d.h       |   2 +-
 riscv/insns/mul_d_rm.h    |   2 +-
 riscv/insns/mul_s.h       |   2 +-
 riscv/insns/mul_s_rm.h    |   2 +-
 riscv/insns/mulh.h        |   2 +-
 riscv/insns/mulhu.h       |   2 +-
 riscv/insns/mulhuw.h      |   2 +-
 riscv/insns/mulhw.h       |   2 +-
 riscv/insns/mulw.h        |   2 +-
 riscv/insns/nmadd_d.h     |   2 +-
 riscv/insns/nmadd_d_rm.h  |   2 +-
 riscv/insns/nmadd_s.h     |   2 +-
 riscv/insns/nmadd_s_rm.h  |   2 +-
 riscv/insns/nmsub_d.h     |   2 +-
 riscv/insns/nmsub_d_rm.h  |   2 +-
 riscv/insns/nmsub_s.h     |   2 +-
 riscv/insns/nmsub_s_rm.h  |   2 +-
 riscv/insns/nor.h         |   2 +-
 riscv/insns/or.h          |   2 +-
 riscv/insns/ori.h         |   2 +-
 riscv/insns/rdnpc.h       |   2 +-
 riscv/insns/rem.h         |   2 +-
 riscv/insns/remu.h        |   2 +-
 riscv/insns/remuw.h       |   2 +-
 riscv/insns/remw.h        |   2 +-
 riscv/insns/s_d.h         |   2 +-
 riscv/insns/s_s.h         |   2 +-
 riscv/insns/sb.h          |   2 +-
 riscv/insns/sd.h          |   2 +-
 riscv/insns/sgninj_d.h    |   2 +-
 riscv/insns/sgninj_s.h    |   2 +-
 riscv/insns/sgninjn_d.h   |   2 +-
 riscv/insns/sgninjn_s.h   |   2 +-
 riscv/insns/sgnmul_d.h    |   2 +-
 riscv/insns/sgnmul_s.h    |   2 +-
 riscv/insns/sh.h          |   2 +-
 riscv/insns/sll.h         |   2 +-
 riscv/insns/slli.h        |   2 +-
 riscv/insns/slliw.h       |   2 +-
 riscv/insns/sllw.h        |   2 +-
 riscv/insns/slt.h         |   2 +-
 riscv/insns/slti.h        |   2 +-
 riscv/insns/sltiu.h       |   2 +-
 riscv/insns/sltu.h        |   2 +-
 riscv/insns/sqrt_d.h      |   2 +-
 riscv/insns/sqrt_d_rm.h   |   2 +-
 riscv/insns/sqrt_s.h      |   2 +-
 riscv/insns/sqrt_s_rm.h   |   2 +-
 riscv/insns/sra.h         |   2 +-
 riscv/insns/srai.h        |   2 +-
 riscv/insns/sraiw.h       |   2 +-
 riscv/insns/sraw.h        |   2 +-
 riscv/insns/srl.h         |   2 +-
 riscv/insns/srli.h        |   2 +-
 riscv/insns/srliw.h       |   2 +-
 riscv/insns/srlw.h        |   2 +-
 riscv/insns/sub.h         |   2 +-
 riscv/insns/sub_d.h       |   2 +-
 riscv/insns/sub_d_rm.h    |   2 +-
 riscv/insns/sub_s.h       |   2 +-
 riscv/insns/sub_s_rm.h    |   2 +-
 riscv/insns/subw.h        |   2 +-
 riscv/insns/sw.h          |   2 +-
 riscv/insns/xor.h         |   2 +-
 riscv/insns/xori.h        |   2 +-
 167 files changed, 517 insertions(+), 513 deletions(-)
 delete mode 100644 riscv/insns/break.h

(limited to 'riscv')

diff --git a/riscv/decode.h b/riscv/decode.h
index 9278a35..327da6c 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -37,6 +37,7 @@ const int FPRID_BITS = 5;
 const int NFPR = 1 << FPRID_BITS;
 
 const int IMM_BITS = 12;
+const int IMMLO_BITS = 5;
 const int TARGET_BITS = 25;
 const int SHAMT_BITS = 6;
 const int FUNCT_BITS = 3;
@@ -83,10 +84,20 @@ const int JUMP_ALIGN_BITS = 1;
 // note: bit fields are in little-endian order
 struct itype_t
 {
+  unsigned rd : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
   signed imm12 : IMM_BITS;
   unsigned funct : FUNCT_BITS;
+  unsigned opcode : OPCODE_BITS;
+};
+
+struct btype_t
+{
+  unsigned immlo : IMMLO_BITS;
   unsigned rs1 : GPRID_BITS;
-  unsigned rdi : GPRID_BITS;
+  unsigned rs2 : GPRID_BITS;
+  signed immhi : IMM_BITS-IMMLO_BITS;
+  unsigned funct : FUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -98,28 +109,28 @@ struct jtype_t
 
 struct rtype_t
 {
-  unsigned rdr : GPRID_BITS;
-  unsigned functr : FUNCTR_BITS;
-  unsigned funct : FUNCT_BITS;
+  unsigned rd : GPRID_BITS;
   unsigned rs1 : GPRID_BITS;
   unsigned rs2 : GPRID_BITS;
+  unsigned functr : FUNCTR_BITS;
+  unsigned funct : FUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
-struct btype_t
+struct ltype_t
 {
+  unsigned rd : GPRID_BITS;
   unsigned bigimm : BIGIMM_BITS;
-  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct ftype_t
 {
-  unsigned rdr : FPRID_BITS;
-  unsigned rs3 : FPRID_BITS;
-  unsigned ffunct : FFUNCT_BITS;
+  unsigned rd  : FPRID_BITS;
   unsigned rs1 : FPRID_BITS;
   unsigned rs2 : FPRID_BITS;
+  unsigned rs3 : FPRID_BITS;
+  unsigned ffunct : FFUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -129,6 +140,7 @@ union insn_t
   jtype_t jtype;
   rtype_t rtype;
   btype_t btype;
+  ltype_t ltype;
   ftype_t ftype;
   uint32_t bits;
 };
@@ -160,21 +172,20 @@ private:
 // helpful macros, etc
 #define RS1 R[insn.rtype.rs1]
 #define RS2 R[insn.rtype.rs2]
-#define RDR do_writeback(R,insn.rtype.rdr)
-#define RDI do_writeback(R,insn.itype.rdi)
+#define RD do_writeback(R,insn.rtype.rd)
 #define FRS1 FR[insn.ftype.rs1]
 #define FRS2 FR[insn.ftype.rs2]
 #define FRS3 FR[insn.ftype.rs3]
-#define FRDR FR[insn.ftype.rdr]
-#define FRDI FR[insn.itype.rdi]
-#define BIGIMM insn.btype.bigimm
+#define FRD FR[insn.ftype.rd]
+#define BIGIMM insn.ltype.bigimm
 #define SIMM insn.itype.imm12
+#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 #define SHAMT (insn.itype.imm12 & 0x3F)
 #define SHAMTW (insn.itype.imm12 & 0x1F)
 #define TARGET insn.jtype.target
-#define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
+#define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
-#define RM ((insn.ftype.ffunct >> 1) & 3)
+#define RM (insn.ftype.ffunct & 3)
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction
diff --git a/riscv/execute.h b/riscv/execute.h
index d80c12f..ae8cfdf 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -3,7 +3,7 @@ switch((insn.bits >> 0x19) & 0x7f)
 {
   case 0x0:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -33,7 +33,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x68:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
@@ -54,7 +54,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x69:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
@@ -75,166 +75,170 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6a:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xd40002a0)
+        if((insn.bits & 0xffff8000) == 0xd40a8000)
         {
           #include "insns/c_eq_s.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000a0)
+        if((insn.bits & 0xffff8000) == 0xd4028000)
         {
           #include "insns/sgninj_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001c0)
+        if((insn.bits & 0xfffffc00) == 0xd4070000)
         {
           #include "insns/cvt_s_w.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005e0)
+        if((insn.bits & 0xffff8000) == 0xd4000000)
         {
-          #include "insns/cvtu_s_w_rm.h"
+          #include "insns/add_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000500)
+        if((insn.bits & 0xffff83e0) == 0xd42c0000)
         {
-          #include "insns/cvt_l_s_rm.h"
+          #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000000)
+        if((insn.bits & 0xfffffc00) == 0xd42e0000)
         {
-          #include "insns/add_s.h"
+          #include "insns/mtf_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005a0)
+        if((insn.bits & 0xffff8000) == 0xd4030000)
         {
-          #include "insns/cvtu_s_l_rm.h"
+          #include "insns/sgninjn_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4000b00)
+        if((insn.bits & 0xfffffc00) == 0xd4078000)
         {
-          #include "insns/mff_s.h"
+          #include "insns/cvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000b80)
+        if((insn.bits & 0xfffffc00) == 0xd4068000)
         {
-          #include "insns/mtf_s.h"
+          #include "insns/cvtu_s_l.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000c0)
+        if((insn.bits & 0xfffffc00) == 0xd4060000)
         {
-          #include "insns/sgninjn_s.h"
+          #include "insns/cvt_s_l.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000440)
+        if((insn.bits & 0xffff8000) == 0xd4008000)
         {
-          #include "insns/mul_s_rm.h"
+          #include "insns/sub_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000520)
+        if((insn.bits & 0xfffffc00) == 0xd4020000)
         {
-          #include "insns/cvtu_l_s_rm.h"
+          #include "insns/sqrt_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005c0)
+        if((insn.bits & 0xffff8000) == 0xd40b0000)
         {
-          #include "insns/cvt_s_w_rm.h"
+          #include "insns/c_lt_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001e0)
+        if((insn.bits & 0xffff8000) == 0xd4038000)
         {
-          #include "insns/cvtu_s_w.h"
+          #include "insns/sgnmul_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001a0)
+        if((insn.bits & 0xffff8000) == 0xd4018000)
         {
-          #include "insns/cvtu_s_l.h"
+          #include "insns/div_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000480)
+        if((insn.bits & 0xfffffc00) == 0xd4098000)
         {
-          #include "insns/sqrt_s_rm.h"
+          #include "insns/cvt_s_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000660)
+        if((insn.bits & 0xffff8000) == 0xd40b8000)
         {
-          #include "insns/cvt_s_d_rm.h"
+          #include "insns/c_le_s.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000420)
+        if((insn.bits & 0xffff8000) == 0xd4010000)
         {
-          #include "insns/sub_s_rm.h"
+          #include "insns/mul_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000180)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xffcffc00) == 0xd4478000)
         {
-          #include "insns/cvt_s_l.h"
+          #include "insns/cvtu_s_w_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000460)
+        if((insn.bits & 0xffcffc00) == 0xd4440000)
         {
-          #include "insns/div_s_rm.h"
+          #include "insns/cvt_l_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000020)
+        if((insn.bits & 0xffcffc00) == 0xd4468000)
         {
-          #include "insns/sub_s.h"
+          #include "insns/cvtu_s_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000580)
+        if((insn.bits & 0xffcf8000) == 0xd4410000)
         {
-          #include "insns/cvt_s_l_rm.h"
+          #include "insns/mul_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000080)
+        if((insn.bits & 0xffcffc00) == 0xd4448000)
         {
-          #include "insns/sqrt_s.h"
+          #include "insns/cvtu_l_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40002c0)
+        if((insn.bits & 0xffcffc00) == 0xd4470000)
         {
-          #include "insns/c_lt_s.h"
+          #include "insns/cvt_s_w_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000400)
+        if((insn.bits & 0xffcffc00) == 0xd4420000)
         {
-          #include "insns/add_s_rm.h"
+          #include "insns/sqrt_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000e0)
+        if((insn.bits & 0xffcffc00) == 0xd4498000)
         {
-          #include "insns/sgnmul_s.h"
+          #include "insns/cvt_s_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000060)
+        if((insn.bits & 0xffcf8000) == 0xd4408000)
         {
-          #include "insns/div_s.h"
+          #include "insns/sub_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000260)
+        if((insn.bits & 0xffcf8000) == 0xd4418000)
         {
-          #include "insns/cvt_s_d.h"
+          #include "insns/div_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40002e0)
+        if((insn.bits & 0xffcffc00) == 0xd4460000)
         {
-          #include "insns/c_le_s.h"
+          #include "insns/cvt_s_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000040)
+        if((insn.bits & 0xffcf8000) == 0xd4400000)
         {
-          #include "insns/mul_s.h"
+          #include "insns/add_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000540)
+        if((insn.bits & 0xffcffc00) == 0xd4450000)
         {
           #include "insns/cvt_w_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000560)
+        if((insn.bits & 0xffcffc00) == 0xd4458000)
         {
           #include "insns/cvtu_w_s_rm.h"
           break;
@@ -243,162 +247,166 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x6:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b00)
+        if((insn.bits & 0xffff83e0) == 0xd5ac0000)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060a0)
+        if((insn.bits & 0xffff8000) == 0xd5828000)
         {
           #include "insns/sgninj_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006580)
-        {
-          #include "insns/cvt_d_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xfe007fe0) == 0xd4006060)
+        if((insn.bits & 0xffff8000) == 0xd5818000)
         {
           #include "insns/div_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062a0)
+        if((insn.bits & 0xffff8000) == 0xd58a8000)
         {
           #include "insns/c_eq_d.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061a0)
+        if((insn.bits & 0xfffffc00) == 0xd5868000)
         {
           #include "insns/cvtu_d_l.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006540)
+        if((insn.bits & 0xfffffc00) == 0xd5878000)
         {
-          #include "insns/cvt_w_d_rm.h"
+          #include "insns/cvtu_d_w.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061e0)
+        if((insn.bits & 0xffff83e0) == 0xd5ac8000)
         {
-          #include "insns/cvtu_d_w.h"
+          #include "insns/mffl_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b20)
+        if((insn.bits & 0xffff8000) == 0xd5838000)
         {
-          #include "insns/mffl_d.h"
+          #include "insns/sgnmul_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006000)
+        if((insn.bits & 0xffff8000) == 0xd5800000)
         {
           #include "insns/add_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b40)
+        if((insn.bits & 0xffff83e0) == 0xd5ad0000)
         {
           #include "insns/mffh_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062e0)
+        if((insn.bits & 0xffff8000) == 0xd58b8000)
         {
           #include "insns/c_le_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060e0)
+        if((insn.bits & 0xffff8000) == 0xd5830000)
         {
-          #include "insns/sgnmul_d.h"
+          #include "insns/sgninjn_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006560)
+        if((insn.bits & 0xffff8000) == 0xd5be0000)
         {
-          #include "insns/cvtu_w_d_rm.h"
+          #include "insns/mtflh_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006480)
+        if((insn.bits & 0xffff8000) == 0xd5808000)
         {
-          #include "insns/sqrt_d_rm.h"
+          #include "insns/sub_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060c0)
+        if((insn.bits & 0xfffffc00) == 0xd5ae0000)
         {
-          #include "insns/sgninjn_d.h"
+          #include "insns/mtf_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40065a0)
+        if((insn.bits & 0xfffffc00) == 0xd5820000)
         {
-          #include "insns/cvtu_d_l_rm.h"
+          #include "insns/sqrt_d.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006400)
+        if((insn.bits & 0xfffffc00) == 0xd5880000)
         {
-          #include "insns/add_d_rm.h"
+          #include "insns/cvt_d_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006500)
+        if((insn.bits & 0xfffffc00) == 0xd5870000)
         {
-          #include "insns/cvt_l_d_rm.h"
+          #include "insns/cvt_d_w.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006f80)
+        if((insn.bits & 0xfffffc00) == 0xd5860000)
         {
-          #include "insns/mtflh_d.h"
+          #include "insns/cvt_d_l.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006520)
+        if((insn.bits & 0xffff8000) == 0xd5810000)
         {
-          #include "insns/cvtu_l_d_rm.h"
+          #include "insns/mul_d.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006440)
+        if((insn.bits & 0xffff8000) == 0xd58b0000)
         {
-          #include "insns/mul_d_rm.h"
+          #include "insns/c_lt_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006020)
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xffcffc00) == 0xd5c60000)
         {
-          #include "insns/sub_d.h"
+          #include "insns/cvt_d_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006b80)
+        if((insn.bits & 0xffcffc00) == 0xd5c50000)
         {
-          #include "insns/mtf_d.h"
+          #include "insns/cvt_w_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006080)
+        if((insn.bits & 0xffcffc00) == 0xd5c58000)
         {
-          #include "insns/sqrt_d.h"
+          #include "insns/cvtu_w_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006460)
+        if((insn.bits & 0xffcffc00) == 0xd5c20000)
         {
-          #include "insns/div_d_rm.h"
+          #include "insns/sqrt_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006200)
+        if((insn.bits & 0xffcffc00) == 0xd5c68000)
         {
-          #include "insns/cvt_d_s.h"
+          #include "insns/cvtu_d_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061c0)
+        if((insn.bits & 0xffcf8000) == 0xd5c00000)
         {
-          #include "insns/cvt_d_w.h"
+          #include "insns/add_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006180)
+        if((insn.bits & 0xffcffc00) == 0xd5c40000)
         {
-          #include "insns/cvt_d_l.h"
+          #include "insns/cvt_l_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006040)
+        if((insn.bits & 0xffcffc00) == 0xd5c48000)
         {
-          #include "insns/mul_d.h"
+          #include "insns/cvtu_l_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062c0)
+        if((insn.bits & 0xffcf8000) == 0xd5c10000)
         {
-          #include "insns/c_lt_d.h"
+          #include "insns/mul_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006420)
+        if((insn.bits & 0xffcf8000) == 0xd5c18000)
+        {
+          #include "insns/div_d_rm.h"
+          break;
+        }
+        if((insn.bits & 0xffcf8000) == 0xd5c08000)
         {
           #include "insns/sub_d_rm.h"
           break;
@@ -412,34 +420,43 @@ switch((insn.bits >> 0x19) & 0x7f)
     }
     break;
   }
-  case 0x6c:
+  case 0x6b:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe006400) == 0xd8000400)
+        if((insn.bits & 0xffffffe0) == 0xd6008000)
         {
-          #include "insns/madd_s_rm.h"
+          #include "insns/di.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xd8000000)
+        if((insn.bits & 0xffffffe0) == 0xd6000000)
         {
-          #include "insns/madd_s.h"
+          #include "insns/ei.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
+      case 0x1:
       {
-        if((insn.bits & 0xfe006400) == 0xd8006400)
+        if((insn.bits & 0xffff83e0) == 0xd6400000)
         {
-          #include "insns/madd_d_rm.h"
+          #include "insns/mfpcr.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xd8006000)
+        if((insn.bits & 0xffff801f) == 0xd6408000)
         {
-          #include "insns/madd_d.h"
+          #include "insns/mtpcr.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xffffffff) == 0xd6800000)
+        {
+          #include "insns/eret.h"
           break;
         }
         #include "insns/unimp.h"
@@ -451,38 +468,77 @@ switch((insn.bits >> 0x19) & 0x7f)
     }
     break;
   }
-  case 0x6d:
+  case 0x6c:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe006400) == 0xda000400)
+        if((insn.bits & 0xfff00000) == 0xd8000000)
         {
-          #include "insns/msub_s_rm.h"
+          #include "insns/madd_s.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xda000000)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        #include "insns/madd_s_rm.h"
+        break;
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff00000) == 0xd9800000)
         {
-          #include "insns/msub_s.h"
+          #include "insns/madd_d.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
+      case 0x7:
       {
-        if((insn.bits & 0xfe007c00) == 0xda006000)
+        #include "insns/madd_d_rm.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
+  case 0x6d:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        if((insn.bits & 0xfff00000) == 0xda000000)
         {
-          #include "insns/msub_d.h"
+          #include "insns/msub_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xda006400)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        #include "insns/msub_s_rm.h"
+        break;
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff00000) == 0xdb800000)
         {
-          #include "insns/msub_d_rm.h"
+          #include "insns/msub_d.h"
           break;
         }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/msub_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -492,36 +548,36 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6e:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007c00) == 0xdc000000)
+        if((insn.bits & 0xfff00000) == 0xdc000000)
         {
           #include "insns/nmsub_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xdc000400)
-        {
-          #include "insns/nmsub_s_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x1:
+      {
+        #include "insns/nmsub_s_rm.h"
+        break;
+      }
       case 0x6:
       {
-        if((insn.bits & 0xfe007c00) == 0xdc006000)
+        if((insn.bits & 0xfff00000) == 0xdd800000)
         {
           #include "insns/nmsub_d.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xdc006400)
-        {
-          #include "insns/nmsub_d_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/nmsub_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -531,36 +587,36 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6f:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007c00) == 0xde000000)
+        if((insn.bits & 0xfff00000) == 0xde000000)
         {
           #include "insns/nmadd_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xde000400)
-        {
-          #include "insns/nmadd_s_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x1:
+      {
+        #include "insns/nmadd_s_rm.h"
+        break;
+      }
       case 0x6:
       {
-        if((insn.bits & 0xfe007c00) == 0xde006000)
+        if((insn.bits & 0xfff00000) == 0xdf800000)
         {
           #include "insns/nmadd_d.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xde006400)
-        {
-          #include "insns/nmadd_d_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/nmadd_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -573,9 +629,35 @@ switch((insn.bits >> 0x19) & 0x7f)
     #include "insns/lui.h"
     break;
   }
+  case 0x72:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        #include "insns/jalr_c.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/jalr_r.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/jalr_j.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x73:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -616,7 +698,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x74:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -650,17 +732,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fc0) == 0xe8007080)
+        if((insn.bits & 0xffff0000) == 0xe9c20000)
         {
           #include "insns/srli.h"
           break;
         }
-        if((insn.bits & 0xfe007fc0) == 0xe80070c0)
+        if((insn.bits & 0xffff0000) == 0xe9c30000)
         {
           #include "insns/srai.h"
           break;
         }
-        if((insn.bits & 0xfe007fc0) == 0xe8007040)
+        if((insn.bits & 0xffff0000) == 0xe9c10000)
         {
           #include "insns/slli.h"
           break;
@@ -676,46 +758,46 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x75:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea000000)
+        if((insn.bits & 0xffff8000) == 0xea000000)
         {
           #include "insns/add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
+        if((insn.bits & 0xffff8000) == 0xea038000)
         {
           #include "insns/nor.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000060)
+        if((insn.bits & 0xffff8000) == 0xea018000)
         {
           #include "insns/sltu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000c0)
+        if((insn.bits & 0xffff8000) == 0xea030000)
         {
           #include "insns/xor.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000020)
+        if((insn.bits & 0xffff8000) == 0xea008000)
         {
           #include "insns/sub.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000a0)
+        if((insn.bits & 0xffff8000) == 0xea028000)
         {
           #include "insns/or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000040)
+        if((insn.bits & 0xffff8000) == 0xea010000)
         {
           #include "insns/slt.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000080)
+        if((insn.bits & 0xffff8000) == 0xea020000)
         {
           #include "insns/and.h"
           break;
@@ -724,37 +806,37 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea001000)
+        if((insn.bits & 0xffff8000) == 0xea400000)
         {
           #include "insns/mul.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001080)
+        if((insn.bits & 0xffff8000) == 0xea420000)
         {
           #include "insns/div.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010c0)
+        if((insn.bits & 0xffff8000) == 0xea430000)
         {
           #include "insns/rem.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001040)
+        if((insn.bits & 0xffff8000) == 0xea410000)
         {
           #include "insns/mulh.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010e0)
+        if((insn.bits & 0xffff8000) == 0xea438000)
         {
           #include "insns/remu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001060)
+        if((insn.bits & 0xffff8000) == 0xea418000)
         {
           #include "insns/mulhu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010a0)
+        if((insn.bits & 0xffff8000) == 0xea428000)
         {
           #include "insns/divu.h"
           break;
@@ -763,17 +845,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea0070c0)
+        if((insn.bits & 0xffff8000) == 0xebc30000)
         {
           #include "insns/sra.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea007080)
+        if((insn.bits & 0xffff8000) == 0xebc20000)
         {
           #include "insns/srl.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea007040)
+        if((insn.bits & 0xffff8000) == 0xebc10000)
         {
           #include "insns/sll.h"
           break;
@@ -789,7 +871,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x76:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -798,17 +880,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec007040)
+        if((insn.bits & 0xffff8000) == 0xedc10000)
         {
           #include "insns/slliw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec007080)
+        if((insn.bits & 0xffff8000) == 0xedc20000)
         {
           #include "insns/srliw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0070c0)
+        if((insn.bits & 0xffff8000) == 0xedc30000)
         {
           #include "insns/sraiw.h"
           break;
@@ -824,16 +906,16 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x77:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee000000)
+        if((insn.bits & 0xffff8000) == 0xee000000)
         {
           #include "insns/addw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee000020)
+        if((insn.bits & 0xffff8000) == 0xee008000)
         {
           #include "insns/subw.h"
           break;
@@ -842,37 +924,37 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee0010e0)
+        if((insn.bits & 0xffff8000) == 0xee438000)
         {
           #include "insns/remuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0010a0)
+        if((insn.bits & 0xffff8000) == 0xee428000)
         {
           #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001060)
+        if((insn.bits & 0xffff8000) == 0xee418000)
         {
           #include "insns/mulhuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001000)
+        if((insn.bits & 0xffff8000) == 0xee400000)
         {
           #include "insns/mulw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0010c0)
+        if((insn.bits & 0xffff8000) == 0xee430000)
         {
           #include "insns/remw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001040)
+        if((insn.bits & 0xffff8000) == 0xee410000)
         {
           #include "insns/mulhw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001080)
+        if((insn.bits & 0xffff8000) == 0xee420000)
         {
           #include "insns/divw.h"
           break;
@@ -881,17 +963,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee007080)
+        if((insn.bits & 0xffff8000) == 0xefc20000)
         {
           #include "insns/srlw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0070c0)
+        if((insn.bits & 0xffff8000) == 0xefc30000)
         {
           #include "insns/sraw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee007040)
+        if((insn.bits & 0xffff8000) == 0xefc10000)
         {
           #include "insns/sllw.h"
           break;
@@ -907,7 +989,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x78:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -946,7 +1028,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfff07000) == 0xf0007000)
+        if((insn.bits & 0xffc0001f) == 0xf1c00000)
         {
           #include "insns/synci.h"
           break;
@@ -962,7 +1044,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x79:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -993,46 +1075,46 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x7a:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
-        if((insn.bits & 0xfe007fe0) == 0xf4002040)
+        if((insn.bits & 0xffff8000) == 0xf4828000)
         {
-          #include "insns/amow_and.h"
+          #include "insns/amow_max.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002080)
+        if((insn.bits & 0xffff8000) == 0xf4810000)
         {
-          #include "insns/amow_min.h"
+          #include "insns/amow_and.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002060)
+        if((insn.bits & 0xffff8000) == 0xf4820000)
         {
-          #include "insns/amow_or.h"
+          #include "insns/amow_min.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020a0)
+        if((insn.bits & 0xffff8000) == 0xf4818000)
         {
-          #include "insns/amow_max.h"
+          #include "insns/amow_or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020c0)
+        if((insn.bits & 0xffff8000) == 0xf4830000)
         {
           #include "insns/amow_minu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002000)
+        if((insn.bits & 0xffff8000) == 0xf4800000)
         {
           #include "insns/amow_add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002020)
+        if((insn.bits & 0xffff8000) == 0xf4808000)
         {
           #include "insns/amow_swap.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020e0)
+        if((insn.bits & 0xffff8000) == 0xf4838000)
         {
           #include "insns/amow_maxu.h"
           break;
@@ -1041,42 +1123,42 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x3:
       {
-        if((insn.bits & 0xfe007fe0) == 0xf4003000)
+        if((insn.bits & 0xffff8000) == 0xf4c00000)
         {
           #include "insns/amo_add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003020)
+        if((insn.bits & 0xffff8000) == 0xf4c08000)
         {
           #include "insns/amo_swap.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003060)
+        if((insn.bits & 0xffff8000) == 0xf4c18000)
         {
           #include "insns/amo_or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030a0)
+        if((insn.bits & 0xffff8000) == 0xf4c28000)
         {
           #include "insns/amo_max.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003080)
+        if((insn.bits & 0xffff8000) == 0xf4c20000)
         {
           #include "insns/amo_min.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030c0)
+        if((insn.bits & 0xffff8000) == 0xf4c30000)
         {
           #include "insns/amo_minu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003040)
+        if((insn.bits & 0xffff8000) == 0xf4c10000)
         {
           #include "insns/amo_and.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030e0)
+        if((insn.bits & 0xffff8000) == 0xf4c38000)
         {
           #include "insns/amo_maxu.h"
           break;
@@ -1092,137 +1174,49 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x7b:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff07fe0) == 0xf6000000)
-        {
-          #include "insns/jalr_c.h"
-          break;
-        }
-        if((insn.bits & 0xfff07fe0) == 0xf6000040)
-        {
-          #include "insns/jalr_j.h"
-          break;
-        }
-        if((insn.bits & 0xfff07fe0) == 0xf6000020)
-        {
-          #include "insns/jalr_r.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        if((insn.bits & 0xffffffe0) == 0xf6001000)
+        if((insn.bits & 0xffffffe0) == 0xf6000000)
         {
           #include "insns/rdnpc.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x2:
+      case 0x1:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        if((insn.bits & 0xffff83e0) == 0xf6400000)
         {
           #include "insns/mfcr.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x3:
-      {
-        if((insn.bits & 0xfe007fff) == 0xf6003000)
+        if((insn.bits & 0xffff801f) == 0xf6408000)
         {
           #include "insns/mtcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x4:
+      case 0x2:
       {
-        if((insn.bits & 0xffffffff) == 0xf6004000)
+        if((insn.bits & 0xffffffff) == 0xf6800000)
         {
           #include "insns/sync.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x5:
+      case 0x3:
       {
-        if((insn.bits & 0xfffff000) == 0xf6005000)
+        if((insn.bits & 0xffc003ff) == 0xf6c00000)
         {
           #include "insns/syscall.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
-      {
-        if((insn.bits & 0xfffff000) == 0xf6006000)
-        {
-          #include "insns/break.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      default:
-      {
-        #include "insns/unimp.h"
-      }
-    }
-    break;
-  }
-  case 0x7e:
-  {
-    switch((insn.bits >> 0xc) & 0x7)
-    {
-      case 0x0:
-      {
-        if((insn.bits & 0xffffffe0) == 0xfc000000)
-        {
-          #include "insns/ei.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        if((insn.bits & 0xffffffe0) == 0xfc001000)
-        {
-          #include "insns/di.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x2:
-      {
-        if((insn.bits & 0xffffffff) == 0xfc002000)
-        {
-          #include "insns/eret.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x4:
-      {
-        if((insn.bits & 0xfe0fffe0) == 0xfc004000)
-        {
-          #include "insns/mfpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x5:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc005000)
-        {
-          #include "insns/mtpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"
diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index f7dede9..a7ec78d 100644
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 + RS2;
+RD = RS1 + RS2;
diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
index eae2c6e..f467eb6 100644
--- a/riscv/insns/add_d.h
+++ b/riscv/insns/add_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_add(FRS1, FRS2);
+FRD = f64_add(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/add_d_rm.h b/riscv/insns/add_d_rm.h
index 2266a31..48c76a7 100644
--- a/riscv/insns/add_d_rm.h
+++ b/riscv/insns/add_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_add(FRS1, FRS2);
+FRD = f64_add(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
index 7c9dc50..edae853 100644
--- a/riscv/insns/add_s.h
+++ b/riscv/insns/add_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_add(FRS1, FRS2);
+FRD = f32_add(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/add_s_rm.h b/riscv/insns/add_s_rm.h
index 2c9730c..2fd5429 100644
--- a/riscv/insns/add_s_rm.h
+++ b/riscv/insns/add_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_add(FRS1, FRS2);
+FRD = f32_add(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index e813eae..2b9bae3 100644
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1,2 @@
 require64;
-RDI = SIMM + RS1;
+RD = SIMM + RS1;
diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 6dfe5b1..cf97d34 100644
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1 @@
-RDI = sext32(SIMM + RS1);
+RD = sext32(SIMM + RS1);
diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index d95c95f..f8715e3 100644
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 + RS2);
+RD = sext32(RS1 + RS2);
 
diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h
index 18f6f4e..3b59ffd 100644
--- a/riscv/insns/amo_add.h
+++ b/riscv/insns/amo_add.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 + v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h
index dd187df..7295501 100644
--- a/riscv/insns/amo_and.h
+++ b/riscv/insns/amo_and.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 & v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
index 296b86a..f67f1a3 100644
--- a/riscv/insns/amo_max.h
+++ b/riscv/insns/amo_max.h
@@ -1,4 +1,4 @@
 require64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h
index 533dde3..9a3d9f6 100644
--- a/riscv/insns/amo_maxu.h
+++ b/riscv/insns/amo_maxu.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::max(RS2,v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
index 7244e87..4acfe74 100644
--- a/riscv/insns/amo_min.h
+++ b/riscv/insns/amo_min.h
@@ -1,4 +1,4 @@
 require64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
index 3e365ab..5af3b9d 100644
--- a/riscv/insns/amo_minu.h
+++ b/riscv/insns/amo_minu.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::min(RS2,v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
index e7d81a8..df4f2fe 100644
--- a/riscv/insns/amo_or.h
+++ b/riscv/insns/amo_or.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 | v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h
index 0ee4ea2..6889055 100644
--- a/riscv/insns/amo_swap.h
+++ b/riscv/insns/amo_swap.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h
index a55ddf9..033b3c8 100644
--- a/riscv/insns/amow_add.h
+++ b/riscv/insns/amow_add.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 + v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h
index f1670bd..18a9249 100644
--- a/riscv/insns/amow_and.h
+++ b/riscv/insns/amow_and.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 & v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h
index c4854d1..ff9c2da 100644
--- a/riscv/insns/amow_max.h
+++ b/riscv/insns/amow_max.h
@@ -1,3 +1,3 @@
 int32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amow_maxu.h
index 37219a8..f7b0b7f 100644
--- a/riscv/insns/amow_maxu.h
+++ b/riscv/insns/amow_maxu.h
@@ -1,3 +1,3 @@
 uint32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_min.h b/riscv/insns/amow_min.h
index ac13623..529ad50 100644
--- a/riscv/insns/amow_min.h
+++ b/riscv/insns/amow_min.h
@@ -1,3 +1,3 @@
 int32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amow_minu.h
index de3ee56..2e9fd17 100644
--- a/riscv/insns/amow_minu.h
+++ b/riscv/insns/amow_minu.h
@@ -1,3 +1,3 @@
 uint32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_or.h b/riscv/insns/amow_or.h
index e569665..741fbef 100644
--- a/riscv/insns/amow_or.h
+++ b/riscv/insns/amow_or.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 | v);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h
index c8b108a..30e6102 100644
--- a/riscv/insns/amow_swap.h
+++ b/riscv/insns/amow_swap.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2);
-RDR = v;
+RD = v;
diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index a63e83f..88ac1d8 100644
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RDR = RS1 & RS2;
+RD = RS1 & RS2;
diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 2c90b8b..5caea16 100644
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RDI = SIMM & RS1;
+RD = SIMM & RS1;
diff --git a/riscv/insns/break.h b/riscv/insns/break.h
deleted file mode 100644
index 7fd3d66..0000000
--- a/riscv/insns/break.h
+++ /dev/null
@@ -1 +0,0 @@
-throw trap_breakpoint;
diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h
index 127e57e..9db8760 100644
--- a/riscv/insns/c_eq_d.h
+++ b/riscv/insns/c_eq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_eq(FRS1, FRS2);
+RD = f64_eq(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
index 0a2ccd9..658e8f6 100644
--- a/riscv/insns/c_eq_s.h
+++ b/riscv/insns/c_eq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_eq(FRS1, FRS2);
+RD = f32_eq(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h
index 23f9703..da76187 100644
--- a/riscv/insns/c_le_d.h
+++ b/riscv/insns/c_le_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_le(FRS1, FRS2);
+RD = f64_le(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
index 7350a9e..9c83a17 100644
--- a/riscv/insns/c_le_s.h
+++ b/riscv/insns/c_le_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_le(FRS1, FRS2);
+RD = f32_le(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h
index 77e7eec..01d135a 100644
--- a/riscv/insns/c_lt_d.h
+++ b/riscv/insns/c_lt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_lt(FRS1, FRS2);
+RD = f64_lt(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
index cdb4372..52eee5d 100644
--- a/riscv/insns/c_lt_s.h
+++ b/riscv/insns/c_lt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_lt(FRS1, FRS2);
+RD = f32_lt(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 8a60e64..28a03a9 100644
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_l_rm.h b/riscv/insns/cvt_d_l_rm.h
index 0e50864..84c1a71 100644
--- a/riscv/insns/cvt_d_l_rm.h
+++ b/riscv/insns/cvt_d_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
index 7a26f70..8e2b2f8 100644
--- a/riscv/insns/cvt_d_s.h
+++ b/riscv/insns/cvt_d_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_to_f64(FRS1);
+FRD = f32_to_f64(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_s_rm.h b/riscv/insns/cvt_d_s_rm.h
index 4c45e30..6b1a09c 100644
--- a/riscv/insns/cvt_d_s_rm.h
+++ b/riscv/insns/cvt_d_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_to_f64(FRS1);
+FRD = f32_to_f64(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index 96acc2b..94cd770 100644
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f64(RS1);
+FRD = i32_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_w_rm.h b/riscv/insns/cvt_d_w_rm.h
index e91945b..638a5ec 100644
--- a/riscv/insns/cvt_d_w_rm.h
+++ b/riscv/insns/cvt_d_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i32_to_f64(RS1);
+FRD = i32_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_l_d_rm.h b/riscv/insns/cvt_l_d_rm.h
index 0d5e7de..2747d67 100644
--- a/riscv/insns/cvt_l_d_rm.h
+++ b/riscv/insns/cvt_l_d_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_l_s_rm.h b/riscv/insns/cvt_l_s_rm.h
index e05f46d..f5b053c 100644
--- a/riscv/insns/cvt_l_s_rm.h
+++ b/riscv/insns/cvt_l_s_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
index 56d6fe3..1c9b281 100644
--- a/riscv/insns/cvt_s_d.h
+++ b/riscv/insns/cvt_s_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_to_f32(FRS1);
+FRD = f64_to_f32(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_d_rm.h b/riscv/insns/cvt_s_d_rm.h
index 4e85fd7..e5289c4 100644
--- a/riscv/insns/cvt_s_d_rm.h
+++ b/riscv/insns/cvt_s_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_to_f32(FRS1);
+FRD = f64_to_f32(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index fe10e85..c89657d 100644
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_l_rm.h b/riscv/insns/cvt_s_l_rm.h
index 9b8d0ca..79fbc97 100644
--- a/riscv/insns/cvt_s_l_rm.h
+++ b/riscv/insns/cvt_s_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index 8501547..b11d783 100644
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f32(RS1);
+FRD = i32_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_w_rm.h b/riscv/insns/cvt_s_w_rm.h
index bfb4f44..12b1e73 100644
--- a/riscv/insns/cvt_s_w_rm.h
+++ b/riscv/insns/cvt_s_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i32_to_f32(RS1);
+FRD = i32_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_w_d_rm.h b/riscv/insns/cvt_w_d_rm.h
index 48db666..e924467 100644
--- a/riscv/insns/cvt_w_d_rm.h
+++ b/riscv/insns/cvt_w_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i32_r_minMag(FRS1,true);
+RD = f64_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvt_w_s_rm.h b/riscv/insns/cvt_w_s_rm.h
index d7bc839..809797f 100644
--- a/riscv/insns/cvt_w_s_rm.h
+++ b/riscv/insns/cvt_w_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i32_r_minMag(FRS1,true);
+RD = f32_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 8a60e64..28a03a9 100644
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_l_rm.h b/riscv/insns/cvtu_d_l_rm.h
index 0e50864..84c1a71 100644
--- a/riscv/insns/cvtu_d_l_rm.h
+++ b/riscv/insns/cvtu_d_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 494f9b0..6a74d2d 100644
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f64(RS1);
+FRD = ui32_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_w_rm.h b/riscv/insns/cvtu_d_w_rm.h
index 9477cbe..2757790 100644
--- a/riscv/insns/cvtu_d_w_rm.h
+++ b/riscv/insns/cvtu_d_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = ui32_to_f64(RS1);
+FRD = ui32_to_f64(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_l_d_rm.h b/riscv/insns/cvtu_l_d_rm.h
index 0d5e7de..2747d67 100644
--- a/riscv/insns/cvtu_l_d_rm.h
+++ b/riscv/insns/cvtu_l_d_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_l_s_rm.h b/riscv/insns/cvtu_l_s_rm.h
index e05f46d..f5b053c 100644
--- a/riscv/insns/cvtu_l_s_rm.h
+++ b/riscv/insns/cvtu_l_s_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index fe10e85..c89657d 100644
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_l_rm.h b/riscv/insns/cvtu_s_l_rm.h
index 9b8d0ca..79fbc97 100644
--- a/riscv/insns/cvtu_s_l_rm.h
+++ b/riscv/insns/cvtu_s_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index fb76e6d..79bb829 100644
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f32(RS1);
+FRD = ui32_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_w_rm.h b/riscv/insns/cvtu_s_w_rm.h
index da521ad..4c53c01 100644
--- a/riscv/insns/cvtu_s_w_rm.h
+++ b/riscv/insns/cvtu_s_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = ui32_to_f32(RS1);
+FRD = ui32_to_f32(RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_w_d_rm.h b/riscv/insns/cvtu_w_d_rm.h
index ef11a51..93860e8 100644
--- a/riscv/insns/cvtu_w_d_rm.h
+++ b/riscv/insns/cvtu_w_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_ui32_r_minMag(FRS1,true);
+RD = f64_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/cvtu_w_s_rm.h b/riscv/insns/cvtu_w_s_rm.h
index 285de4f..04b8fb2 100644
--- a/riscv/insns/cvtu_w_s_rm.h
+++ b/riscv/insns/cvtu_w_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_ui32_r_minMag(FRS1,true);
+RD = f32_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;
diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index 0f3adf9..31280d5 100644
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RDR = temp;
+RD = temp;
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 2d6edfc..9b752aa 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) / sreg_t(RS2);
+RD = sreg_t(RS1) / sreg_t(RS2);
diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 9902da6..9f756f0 100644
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_div(FRS1, FRS2);
+FRD = f64_div(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/div_d_rm.h b/riscv/insns/div_d_rm.h
index 1d92903..aa00c98 100644
--- a/riscv/insns/div_d_rm.h
+++ b/riscv/insns/div_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_div(FRS1, FRS2);
+FRD = f64_div(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index 99e343c..e70d085 100644
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_div(FRS1, FRS2);
+FRD = f32_div(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/div_s_rm.h b/riscv/insns/div_s_rm.h
index 07c8794..8c76587 100644
--- a/riscv/insns/div_s_rm.h
+++ b/riscv/insns/div_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_div(FRS1, FRS2);
+FRD = f32_div(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 35eee14..f1b65fd 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 / RS2;
+RD = RS1 / RS2;
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index f52fe5a..46f7814 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,2 @@
-RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
+RD = sext32(uint32_t(RS1)/uint32_t(RS2));
 
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 938478c..0654b49 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,2 @@
-RDR = sext32(int32_t(RS1)/int32_t(RS2));
+RD = sext32(int32_t(RS1)/int32_t(RS2));
 
diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index f3e5207..8306aeb 100644
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RDR = temp;
+RD = temp;
diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
index dade874..d835b87 100644
--- a/riscv/insns/jalr_c.h
+++ b/riscv/insns/jalr_c.h
@@ -1,3 +1,3 @@
-uint32_t temp = npc;
+uint32_t temp = npc + SIMM;
 npc = RS1;
-RDR = temp;
+RD = temp;
diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
index 8a06e3d..123dea4 100644
--- a/riscv/insns/l_d.h
+++ b/riscv/insns/l_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDI = mmu.load_int64(RS1+SIMM);
+FRD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/l_s.h b/riscv/insns/l_s.h
index 1e9bbf7..335fd7d 100644
--- a/riscv/insns/l_s.h
+++ b/riscv/insns/l_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDI = mmu.load_int32(RS1+SIMM);
+FRD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 47e03d7..81ba7de 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RDI = mmu.load_int8(RS1+SIMM);
+RD = mmu.load_int8(RS1+SIMM);
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index e378871..12c688a 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RDI = mmu.load_uint8(RS1+SIMM);
+RD = mmu.load_uint8(RS1+SIMM);
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 9959d26..973a8b3 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RDI = mmu.load_int64(RS1+SIMM);
+RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index 830b673..ec25bc4 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RDI = mmu.load_int16(RS1+SIMM);
+RD = mmu.load_int16(RS1+SIMM);
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 961c427..0999c00 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RDI = mmu.load_uint16(RS1+SIMM);
+RD = mmu.load_uint16(RS1+SIMM);
diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 20a0af8..6af2a2a 100644
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RDI = sext32(BIGIMM << IMM_BITS);
+RD = sext32(BIGIMM << IMM_BITS);
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 6bd2646..769c9fd 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RDI = mmu.load_int32(RS1+SIMM);
+RD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 3c597af..5e62b0f 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RDI = mmu.load_uint32(RS1+SIMM);
+RD = mmu.load_uint32(RS1+SIMM);
diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h
index c9d6318..41de613 100644
--- a/riscv/insns/madd_d.h
+++ b/riscv/insns/madd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;
diff --git a/riscv/insns/madd_d_rm.h b/riscv/insns/madd_d_rm.h
index ca5d178..f67853e 100644
--- a/riscv/insns/madd_d_rm.h
+++ b/riscv/insns/madd_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;
diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h
index 49f4861..ee26e3c 100644
--- a/riscv/insns/madd_s.h
+++ b/riscv/insns/madd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;
diff --git a/riscv/insns/madd_s_rm.h b/riscv/insns/madd_s_rm.h
index 39eaab6..19db642 100644
--- a/riscv/insns/madd_s_rm.h
+++ b/riscv/insns/madd_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;
diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 1c7ec2d..78b71d0 100644
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -14,4 +14,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RDR = gprlen == 64 ? val : sext32(val);
+RD = gprlen == 64 ? val : sext32(val);
diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index 436043c..ba53561 100644
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RDR = FRS2;
+RD = FRS2;
diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
index 4fdb7df..589b33b 100644
--- a/riscv/insns/mff_s.h
+++ b/riscv/insns/mff_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2);
+RD = sext32(FRS2);
diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h
index 59f6476..78b5423 100644
--- a/riscv/insns/mffh_d.h
+++ b/riscv/insns/mffh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2 >> 32);
+RD = sext32(FRS2 >> 32);
diff --git a/riscv/insns/mffl_d.h b/riscv/insns/mffl_d.h
index 4fdb7df..589b33b 100644
--- a/riscv/insns/mffl_d.h
+++ b/riscv/insns/mffl_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2);
+RD = sext32(FRS2);
diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 704e37b..54c62ed 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -45,4 +45,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RDR = gprlen == 64 ? val : sext32(val);
+RD = gprlen == 64 ? val : sext32(val);
diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h
index 939baca..f3da451 100644
--- a/riscv/insns/msub_d.h
+++ b/riscv/insns/msub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;
diff --git a/riscv/insns/msub_d_rm.h b/riscv/insns/msub_d_rm.h
index 597c779..b1e9340 100644
--- a/riscv/insns/msub_d_rm.h
+++ b/riscv/insns/msub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;
diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h
index b808951..170e1a1 100644
--- a/riscv/insns/msub_s.h
+++ b/riscv/insns/msub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;
diff --git a/riscv/insns/msub_s_rm.h b/riscv/insns/msub_s_rm.h
index 5ff5d59..d3349f5 100644
--- a/riscv/insns/msub_s_rm.h
+++ b/riscv/insns/msub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;
diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 6777689..44daa9e 100644
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRDR = RS1;
+FRD = RS1;
diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
index a1c22fd..54546ea 100644
--- a/riscv/insns/mtf_s.h
+++ b/riscv/insns/mtf_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = RS1;
+FRD = RS1;
diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h
index c48c726..ed4014e 100644
--- a/riscv/insns/mtflh_d.h
+++ b/riscv/insns/mtflh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);
+FRD = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);
diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 226873f..ff1e034 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 * RS2;
+RD = RS1 * RS2;
diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
index 75c7b94..6038728 100644
--- a/riscv/insns/mul_d.h
+++ b/riscv/insns/mul_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mul(FRS1, FRS2);
+FRD = f64_mul(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/mul_d_rm.h b/riscv/insns/mul_d_rm.h
index 3c938da..a8adedd 100644
--- a/riscv/insns/mul_d_rm.h
+++ b/riscv/insns/mul_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mul(FRS1, FRS2);
+FRD = f64_mul(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index 5c1397c..3a5905b 100644
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mul(FRS1, FRS2);
+FRD = f32_mul(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/mul_s_rm.h b/riscv/insns/mul_s_rm.h
index a5bf23a..6475578 100644
--- a/riscv/insns/mul_s_rm.h
+++ b/riscv/insns/mul_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mul(FRS1, FRS2);
+FRD = f32_mul(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index c4fead2..ed9c1a8 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,4 +1,4 @@
 require64;
 int64_t rb = RS1;
 int64_t ra = RS2;
-RDR = (int128_t(rb) * int128_t(ra)) >> 64;
+RD = (int128_t(rb) * int128_t(ra)) >> 64;
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 1ce0252..17c610d 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
index c2a082d..9260a24 100644
--- a/riscv/insns/mulhuw.h
+++ b/riscv/insns/mulhuw.h
@@ -1,2 +1,2 @@
-RDR = sext32((RS1 * RS2) >> 32);
+RD = sext32((RS1 * RS2) >> 32);
 
diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
index 7becbfe..a47aa1e 100644
--- a/riscv/insns/mulhw.h
+++ b/riscv/insns/mulhw.h
@@ -1,2 +1,2 @@
-RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
+RD = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
 
diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index c483fb6..81285a2 100644
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 * RS2);
+RD = sext32(RS1 * RS2);
 
diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h
index 1cdebd3..3d6ac52 100644
--- a/riscv/insns/nmadd_d.h
+++ b/riscv/insns/nmadd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmadd_d_rm.h b/riscv/insns/nmadd_d_rm.h
index 2d4022d..1e2ee27 100644
--- a/riscv/insns/nmadd_d_rm.h
+++ b/riscv/insns/nmadd_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h
index b0b7021..aa05b50 100644
--- a/riscv/insns/nmadd_s.h
+++ b/riscv/insns/nmadd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmadd_s_rm.h b/riscv/insns/nmadd_s_rm.h
index 611653c..78abb78 100644
--- a/riscv/insns/nmadd_s_rm.h
+++ b/riscv/insns/nmadd_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
index 1e010c8..fa4a862 100644
--- a/riscv/insns/nmsub_d.h
+++ b/riscv/insns/nmsub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmsub_d_rm.h b/riscv/insns/nmsub_d_rm.h
index df153b8..ae643a5 100644
--- a/riscv/insns/nmsub_d_rm.h
+++ b/riscv/insns/nmsub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h
index 9818dc7..98442f8 100644
--- a/riscv/insns/nmsub_s.h
+++ b/riscv/insns/nmsub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nmsub_s_rm.h b/riscv/insns/nmsub_s_rm.h
index 02216c9..cbb70ba 100644
--- a/riscv/insns/nmsub_s_rm.h
+++ b/riscv/insns/nmsub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;
diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index a3ba7d1..553449f 100644
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RDR = ~(RS1 | RS2);
+RD = ~(RS1 | RS2);
diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index ef27ba6..07bcac3 100644
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RDR = RS1 | RS2;
+RD = RS1 | RS2;
diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 3ee429d..9561b97 100644
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RDI = SIMM | RS1;
+RD = SIMM | RS1;
diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h
index 254512c..5525421 100644
--- a/riscv/insns/rdnpc.h
+++ b/riscv/insns/rdnpc.h
@@ -1 +1 @@
-RDR = npc;
+RD = npc;
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 9192428..1c82b95 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) % sreg_t(RS2);
+RD = sreg_t(RS1) % sreg_t(RS2);
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 2f40aaa..e6af512 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 % RS2;
+RD = RS1 % RS2;
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 26decf2..0a7a1ba 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,2 @@
-RDR = sext32(uint32_t(RS1) % uint32_t(RS2));
+RD = sext32(uint32_t(RS1) % uint32_t(RS2));
 
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 83bf147..0d67c88 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,2 @@
-RDR = sext32(int32_t(RS1) % int32_t(RS2));
+RD = sext32(int32_t(RS1) % int32_t(RS2));
 
diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index 4c9c466..113398e 100644
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint64(RS1+SIMM, FRS2);
+mmu.store_uint64(RS1+BIMM, FRS2);
diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h
index 384246f..23d3333 100644
--- a/riscv/insns/s_s.h
+++ b/riscv/insns/s_s.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint32(RS1+SIMM, FRS2);
+mmu.store_uint32(RS1+BIMM, FRS2);
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index 5a2110f..af5bd10 100644
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS1+SIMM, RS2);
+mmu.store_uint8(RS1+BIMM, RS2);
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 587df8d..f4ece21 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RS1+SIMM, RS2);
+mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h
index b1722da..f66e804 100644
--- a/riscv/insns/sgninj_d.h
+++ b/riscv/insns/sgninj_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
+FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h
index 2df0b94..35609ac 100644
--- a/riscv/insns/sgninj_s.h
+++ b/riscv/insns/sgninj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h
index 90c7ae9..22de215 100644
--- a/riscv/insns/sgninjn_d.h
+++ b/riscv/insns/sgninjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
+FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h
index 7be7b46..dd66d71 100644
--- a/riscv/insns/sgninjn_s.h
+++ b/riscv/insns/sgninjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h
index 8e55850..331b6e4 100644
--- a/riscv/insns/sgnmul_d.h
+++ b/riscv/insns/sgnmul_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = FRS1 ^ (FRS2 & INT64_MIN);
+FRD = FRS1 ^ (FRS2 & INT64_MIN);
diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h
index e651888..b455406 100644
--- a/riscv/insns/sgnmul_s.h
+++ b/riscv/insns/sgnmul_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
+FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index bbc2bda..a484e1e 100644
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RS1+SIMM, RS2);
+mmu.store_uint16(RS1+BIMM, RS2);
diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 8b6bc70..ae38f16 100644
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 << (RS2 & 0x3F);
+RD = RS1 << (RS2 & 0x3F);
diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 33e23aa..f7ba310 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,2 @@
 require64;
-RDI = RS1 << SHAMT;
+RD = RS1 << SHAMT;
diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 8546977..41be30f 100644
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1 +1 @@
-RDI = sext32(RS1 << SHAMTW);
+RD = sext32(RS1 << SHAMTW);
diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 521c0f7..90e5c4c 100644
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1 @@
-RDR = sext32(RS1 << (RS2 & 0x1F));
+RD = sext32(RS1 << (RS2 & 0x1F));
diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 6511f42..5c50534 100644
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RDR = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 6204619..1dcd892 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RDI = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index b7c8ce6..45e579b 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RDI = cmp_trunc(RS1) < cmp_trunc(SIMM);
+RD = cmp_trunc(RS1) < cmp_trunc(SIMM);
diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 1d4ebe6..2c5bdc3 100644
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RDR = cmp_trunc(RS1) < cmp_trunc(RS2);
+RD = cmp_trunc(RS1) < cmp_trunc(RS2);
diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
index 99ffa18..e2a2014 100644
--- a/riscv/insns/sqrt_d.h
+++ b/riscv/insns/sqrt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_sqrt(FRS1);
+FRD = f64_sqrt(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/sqrt_d_rm.h b/riscv/insns/sqrt_d_rm.h
index 5e93b27..7647c9c 100644
--- a/riscv/insns/sqrt_d_rm.h
+++ b/riscv/insns/sqrt_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_sqrt(FRS1);
+FRD = f64_sqrt(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
index 12c8160..c491649 100644
--- a/riscv/insns/sqrt_s.h
+++ b/riscv/insns/sqrt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_sqrt(FRS1);
+FRD = f32_sqrt(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/sqrt_s_rm.h b/riscv/insns/sqrt_s_rm.h
index cb3ff53..426f241 100644
--- a/riscv/insns/sqrt_s_rm.h
+++ b/riscv/insns/sqrt_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_sqrt(FRS1);
+FRD = f32_sqrt(FRS1);
 set_fp_exceptions;
diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index f0919ba..4a78916 100644
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) >> (RS2 & 0x3F);
+RD = sreg_t(RS1) >> (RS2 & 0x3F);
diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index b2026bb..1f0dde2 100644
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,2 @@
 require64;
-RDI = sreg_t(RS1) >> SHAMT;
+RD = sreg_t(RS1) >> SHAMT;
diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 0831b14..24a9eae 100644
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1 @@
-RDI = sext32(sreg_t(RS1) >> SHAMTW);
+RD = sext32(sreg_t(RS1) >> SHAMTW);
diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index a49ead6..f8946fb 100644
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1 @@
-RDR = sext32(sreg_t(RS1) >> (RS2 & 0x1F));
+RD = sext32(sreg_t(RS1) >> (RS2 & 0x1F));
diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index fa17eb7..87138da 100644
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 >> (RS2 & 0x3F);
+RD = RS1 >> (RS2 & 0x3F);
diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index 29a97a2..e0d8ae0 100644
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
 require64;
-RDI = RS1 >> SHAMT;
+RD = RS1 >> SHAMT;
diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 5513a5a..2a2bb31 100644
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1 +1 @@
-RDI = sext32((uint32_t)RS1 >> SHAMTW);
+RD = sext32((uint32_t)RS1 >> SHAMTW);
diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 7aa4bc6..a0058ae 100644
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RDR = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 005b66f..e7736c9 100644
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 - RS2;
+RD = RS1 - RS2;
diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
index 2099732..54630a2 100644
--- a/riscv/insns/sub_d.h
+++ b/riscv/insns/sub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_sub(FRS1, FRS2);
+FRD = f64_sub(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/sub_d_rm.h b/riscv/insns/sub_d_rm.h
index 85477ef..e25eebb 100644
--- a/riscv/insns/sub_d_rm.h
+++ b/riscv/insns/sub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_sub(FRS1, FRS2);
+FRD = f64_sub(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index e28f042..142c7ab 100644
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_sub(FRS1, FRS2);
+FRD = f32_sub(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/sub_s_rm.h b/riscv/insns/sub_s_rm.h
index 0e9ccf2..6c64d04 100644
--- a/riscv/insns/sub_s_rm.h
+++ b/riscv/insns/sub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_sub(FRS1, FRS2);
+FRD = f32_sub(FRS1, FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 9dd7114..958cc5d 100644
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 - RS2);
+RD = sext32(RS1 - RS2);
 
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index e644e16..dbe260f 100644
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(RS1+SIMM, RS2);
+mmu.store_uint32(RS1+BIMM, RS2);
diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index f11738a..49b1783 100644
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RDR = RS1 ^ RS2;
+RD = RS1 ^ RS2;
diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 039e1b7..5852aac 100644
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RDI = SIMM ^ RS1;
+RD = SIMM ^ RS1;
-- 
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