From 99cb603973b3f9575b411b80934035f3ee7fbcf3 Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 30 Sep 2022 12:01:09 +0800 Subject: Fix priority of mcontrol trigger load address before The spec defines the mcontrol load address has a higher priority over page fault and address misaligned (Debug spec, Table 5.2). Thus, the trigger checking should be before the translation and alignment checking. The previous implementation checks the trigger after the translation and alignment, resulting in incorrect priority. For instance, when page fault and trigger occur on the same instruction, the previous implementation will choose to raise the page fault, which contradicts the priority requirement. This commit adds an address-only trigger checking before the misaligned checking and translation. The trigger will fire on the instruction instead of the page fault in the above case. --- riscv/mmu.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'riscv/mmu.cc') diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 0dbb94e..3048bde 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -141,6 +141,13 @@ bool mmu_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) { + if (!matched_trigger) { + reg_t data = reg_from_bytes(len, bytes); + matched_trigger = trigger_exception(triggers::OPERATION_LOAD, addr, false); + if (matched_trigger) + throw *matched_trigger; + } + reg_t paddr = translate(addr, len, LOAD, xlate_flags); if (auto host_addr = sim->addr_to_mem(paddr)) { -- cgit v1.1