From 9258b59e67f92332fe057e4856e3e2f07312bfe5 Mon Sep 17 00:00:00 2001 From: brs Date: Wed, 18 Oct 2023 19:07:45 -0500 Subject: Spike support for the Zalasr extension --- disasm/disasm.cc | 11 +++++ disasm/isa_parser.cc | 2 + riscv/encoding.h | 136 ++++++++++----------------------------------------- riscv/insns/lb_aq.h | 2 + riscv/insns/ld_aq.h | 3 ++ riscv/insns/lh_aq.h | 2 + riscv/insns/lw_aq.h | 2 + riscv/insns/sb_rl.h | 2 + riscv/insns/sd_rl.h | 3 ++ riscv/insns/sh_rl.h | 2 + riscv/insns/sw_rl.h | 2 + riscv/isa_parser.h | 1 + riscv/riscv.mk.in | 11 +++++ 13 files changed, 69 insertions(+), 110 deletions(-) create mode 100644 riscv/insns/lb_aq.h create mode 100644 riscv/insns/ld_aq.h create mode 100644 riscv/insns/lh_aq.h create mode 100644 riscv/insns/lw_aq.h create mode 100644 riscv/insns/sb_rl.h create mode 100644 riscv/insns/sd_rl.h create mode 100644 riscv/insns/sh_rl.h create mode 100644 riscv/insns/sw_rl.h diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 4f9937f..df02e03 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2304,6 +2304,17 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_VECTOR_VIU(vsm3c_vi); DEFINE_VECTOR_VV(vsm3me_vv); } + + if (isa->extension_enabled(EXT_ZALASR)) { + DEFINE_XLOAD_BASE(lb_aq); + DEFINE_XLOAD_BASE(lh_aq); + DEFINE_XLOAD_BASE(lw_aq); + DEFINE_XLOAD_BASE(ld_aq); + DEFINE_XSTORE_BASE(sb_rl); + DEFINE_XSTORE_BASE(sh_rl); + DEFINE_XSTORE_BASE(sw_rl); + DEFINE_XSTORE_BASE(sd_rl); + } } disassembler_t::disassembler_t(const isa_parser_t *isa) diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index 3291f7d..563f687 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -294,6 +294,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SMCNTRPMF] = true; } else if (ext_str == "zcmop") { extension_table[EXT_ZCMOP] = true; + } else if (ext_str == "zalasr") { + extension_table[EXT_ZALASR] = true; } else if (ext_str[0] == 'x') { extension_table['X'] = true; if (ext_str.size() == 1) { diff --git a/riscv/encoding.h b/riscv/encoding.h index 6ad1fcc..1a0f554 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (b9d63ad) + * https://github.com/riscv/riscv-opcodes (4f28129) */ #ifndef RISCV_CSR_ENCODING_H @@ -1386,14 +1386,20 @@ #define MASK_KWMMUL_U 0xfe00707f #define MATCH_LB 0x3 #define MASK_LB 0x707f +#define MATCH_LB_AQ 0x3000002f +#define MASK_LB_AQ 0xf9f0707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f #define MATCH_LD 0x3003 #define MASK_LD 0x707f +#define MATCH_LD_AQ 0x3000302f +#define MASK_LD_AQ 0xf9f0707f #define MATCH_LDU 0x7003 #define MASK_LDU 0x707f #define MATCH_LH 0x1003 #define MASK_LH 0x707f +#define MATCH_LH_AQ 0x3000102f +#define MASK_LH_AQ 0xf9f0707f #define MATCH_LHU 0x5003 #define MASK_LHU 0x707f #define MATCH_LQ 0x300f @@ -1406,6 +1412,8 @@ #define MASK_LUI 0x7f #define MATCH_LW 0x2003 #define MASK_LW 0x707f +#define MATCH_LW_AQ 0x3000202f +#define MASK_LW_AQ 0xf9f0707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f #define MATCH_MADDR32 0xc4001077 @@ -1620,6 +1628,8 @@ #define MASK_RSUBW 0xfe00707f #define MATCH_SB 0x23 #define MASK_SB 0x707f +#define MATCH_SB_RL 0x3800002f +#define MASK_SB_RL 0xf8007fff #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f #define MATCH_SC_W 0x1800202f @@ -1640,6 +1650,8 @@ #define MASK_SCMPLT8 0xfe00707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f +#define MATCH_SD_RL 0x3800302f +#define MASK_SD_RL 0xf8007fff #define MATCH_SEXT_B 0x60401013 #define MASK_SEXT_B 0xfff0707f #define MATCH_SEXT_H 0x60501013 @@ -1664,6 +1676,8 @@ #define MASK_SH3ADD 0xfe00707f #define MATCH_SH3ADD_UW 0x2000603b #define MASK_SH3ADD_UW 0xfe00707f +#define MATCH_SH_RL 0x3800102f +#define MASK_SH_RL 0xf8007fff #define MATCH_SHA256SIG0 0x10201013 #define MASK_SHA256SIG0 0xfff0707f #define MATCH_SHA256SIG1 0x10301013 @@ -1970,6 +1984,8 @@ #define MASK_SUNPKD832 0xfff0707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f +#define MATCH_SW_RL 0x3800202f +#define MASK_SW_RL 0xf8007fff #define MATCH_UCLIP16 0x85000077 #define MASK_UCLIP16 0xff00707f #define MATCH_UCLIP32 0xf4000077 @@ -2138,78 +2154,6 @@ #define MASK_VAESKF2_VI 0xfe00707f #define MATCH_VAESZ_VS 0xa603a077 #define MASK_VAESZ_VS 0xfe0ff07f -#define MATCH_VAMOADDEI16_V 0x502f -#define MASK_VAMOADDEI16_V 0xf800707f -#define MATCH_VAMOADDEI32_V 0x602f -#define MASK_VAMOADDEI32_V 0xf800707f -#define MATCH_VAMOADDEI64_V 0x702f -#define MASK_VAMOADDEI64_V 0xf800707f -#define MATCH_VAMOADDEI8_V 0x2f -#define MASK_VAMOADDEI8_V 0xf800707f -#define MATCH_VAMOANDEI16_V 0x6000502f -#define MASK_VAMOANDEI16_V 0xf800707f -#define MATCH_VAMOANDEI32_V 0x6000602f -#define MASK_VAMOANDEI32_V 0xf800707f -#define MATCH_VAMOANDEI64_V 0x6000702f -#define MASK_VAMOANDEI64_V 0xf800707f -#define MATCH_VAMOANDEI8_V 0x6000002f -#define MASK_VAMOANDEI8_V 0xf800707f -#define MATCH_VAMOMAXEI16_V 0xa000502f -#define MASK_VAMOMAXEI16_V 0xf800707f -#define MATCH_VAMOMAXEI32_V 0xa000602f -#define MASK_VAMOMAXEI32_V 0xf800707f -#define MATCH_VAMOMAXEI64_V 0xa000702f -#define MASK_VAMOMAXEI64_V 0xf800707f -#define MATCH_VAMOMAXEI8_V 0xa000002f -#define MASK_VAMOMAXEI8_V 0xf800707f -#define MATCH_VAMOMAXUEI16_V 0xe000502f -#define MASK_VAMOMAXUEI16_V 0xf800707f -#define MATCH_VAMOMAXUEI32_V 0xe000602f -#define MASK_VAMOMAXUEI32_V 0xf800707f -#define MATCH_VAMOMAXUEI64_V 0xe000702f -#define MASK_VAMOMAXUEI64_V 0xf800707f -#define MATCH_VAMOMAXUEI8_V 0xe000002f -#define MASK_VAMOMAXUEI8_V 0xf800707f -#define MATCH_VAMOMINEI16_V 0x8000502f -#define MASK_VAMOMINEI16_V 0xf800707f -#define MATCH_VAMOMINEI32_V 0x8000602f -#define MASK_VAMOMINEI32_V 0xf800707f -#define MATCH_VAMOMINEI64_V 0x8000702f -#define MASK_VAMOMINEI64_V 0xf800707f -#define MATCH_VAMOMINEI8_V 0x8000002f -#define MASK_VAMOMINEI8_V 0xf800707f -#define MATCH_VAMOMINUEI16_V 0xc000502f -#define MASK_VAMOMINUEI16_V 0xf800707f -#define MATCH_VAMOMINUEI32_V 0xc000602f -#define MASK_VAMOMINUEI32_V 0xf800707f -#define MATCH_VAMOMINUEI64_V 0xc000702f -#define MASK_VAMOMINUEI64_V 0xf800707f -#define MATCH_VAMOMINUEI8_V 0xc000002f -#define MASK_VAMOMINUEI8_V 0xf800707f -#define MATCH_VAMOOREI16_V 0x4000502f -#define MASK_VAMOOREI16_V 0xf800707f -#define MATCH_VAMOOREI32_V 0x4000602f -#define MASK_VAMOOREI32_V 0xf800707f -#define MATCH_VAMOOREI64_V 0x4000702f -#define MASK_VAMOOREI64_V 0xf800707f -#define MATCH_VAMOOREI8_V 0x4000002f -#define MASK_VAMOOREI8_V 0xf800707f -#define MATCH_VAMOSWAPEI16_V 0x800502f -#define MASK_VAMOSWAPEI16_V 0xf800707f -#define MATCH_VAMOSWAPEI32_V 0x800602f -#define MASK_VAMOSWAPEI32_V 0xf800707f -#define MATCH_VAMOSWAPEI64_V 0x800702f -#define MASK_VAMOSWAPEI64_V 0xf800707f -#define MATCH_VAMOSWAPEI8_V 0x800002f -#define MASK_VAMOSWAPEI8_V 0xf800707f -#define MATCH_VAMOXOREI16_V 0x2000502f -#define MASK_VAMOXOREI16_V 0xf800707f -#define MATCH_VAMOXOREI32_V 0x2000602f -#define MASK_VAMOXOREI32_V 0xf800707f -#define MATCH_VAMOXOREI64_V 0x2000702f -#define MASK_VAMOXOREI64_V 0xf800707f -#define MATCH_VAMOXOREI8_V 0x2000002f -#define MASK_VAMOXOREI8_V 0xf800707f #define MATCH_VAND_VI 0x24003057 #define MASK_VAND_VI 0xfc00707f #define MATCH_VAND_VV 0x24000057 @@ -3603,7 +3547,6 @@ #define INSN_FIELD_BIMM12HI 0xfe000000 #define INSN_FIELD_IMM12LO 0xf80 #define INSN_FIELD_BIMM12LO 0xf80 -#define INSN_FIELD_ZIMM 0xf8000 #define INSN_FIELD_SHAMTQ 0x7f00000 #define INSN_FIELD_SHAMTW 0x1f00000 #define INSN_FIELD_SHAMTW4 0xf00000 @@ -3616,6 +3559,7 @@ #define INSN_FIELD_IMM4 0xf00000 #define INSN_FIELD_IMM5 0x1f00000 #define INSN_FIELD_IMM6 0x3f00000 +#define INSN_FIELD_ZIMM 0xf8000 #define INSN_FIELD_OPCODE 0x7f #define INSN_FIELD_FUNCT7 0xfe000000 #define INSN_FIELD_VD 0xf80 @@ -4191,16 +4135,20 @@ DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lb_aq, MATCH_LB_AQ, MASK_LB_AQ) DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(ld_aq, MATCH_LD_AQ, MASK_LD_AQ) DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU) DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lh_aq, MATCH_LH_AQ, MASK_LH_AQ) DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) DECLARE_INSN(lq, MATCH_LQ, MASK_LQ) DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lw_aq, MATCH_LW_AQ, MASK_LW_AQ) DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) DECLARE_INSN(max, MATCH_MAX, MASK_MAX) @@ -4308,6 +4256,7 @@ DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sb_rl, MATCH_SB_RL, MASK_SB_RL) DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) @@ -4318,6 +4267,7 @@ DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(sd_rl, MATCH_SD_RL, MASK_SD_RL) DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) @@ -4330,6 +4280,7 @@ DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) +DECLARE_INSN(sh_rl, MATCH_SH_RL, MASK_SH_RL) DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) @@ -4483,6 +4434,7 @@ DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sw_rl, MATCH_SW_RL, MASK_SW_RL) DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) @@ -4567,42 +4519,6 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV) DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) -DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) -DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) -DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) -DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) -DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) -DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) -DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) -DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) -DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) -DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) -DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) -DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) -DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) -DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) -DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) -DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) -DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) -DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) -DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) -DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) -DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) -DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) -DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) -DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) -DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) -DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) -DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) -DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) -DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) -DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) -DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) -DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) -DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) -DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) -DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) -DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) diff --git a/riscv/insns/lb_aq.h b/riscv/insns/lb_aq.h new file mode 100644 index 0000000..84423de --- /dev/null +++ b/riscv/insns/lb_aq.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +WRITE_RD(MMU.load(RS1)); diff --git a/riscv/insns/ld_aq.h b/riscv/insns/ld_aq.h new file mode 100644 index 0000000..3c5bae6 --- /dev/null +++ b/riscv/insns/ld_aq.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZALASR); +WRITE_RD(MMU.load(RS1)); diff --git a/riscv/insns/lh_aq.h b/riscv/insns/lh_aq.h new file mode 100644 index 0000000..e018503 --- /dev/null +++ b/riscv/insns/lh_aq.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +WRITE_RD(MMU.load(RS1)); diff --git a/riscv/insns/lw_aq.h b/riscv/insns/lw_aq.h new file mode 100644 index 0000000..88917b5 --- /dev/null +++ b/riscv/insns/lw_aq.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +WRITE_RD(MMU.load(RS1)); diff --git a/riscv/insns/sb_rl.h b/riscv/insns/sb_rl.h new file mode 100644 index 0000000..91d4d25 --- /dev/null +++ b/riscv/insns/sb_rl.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +MMU.store(RS1, RS2); diff --git a/riscv/insns/sd_rl.h b/riscv/insns/sd_rl.h new file mode 100644 index 0000000..980844c --- /dev/null +++ b/riscv/insns/sd_rl.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZALASR); +MMU.store(RS1, RS2); diff --git a/riscv/insns/sh_rl.h b/riscv/insns/sh_rl.h new file mode 100644 index 0000000..bd81cf1 --- /dev/null +++ b/riscv/insns/sh_rl.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +MMU.store(RS1, RS2); diff --git a/riscv/insns/sw_rl.h b/riscv/insns/sw_rl.h new file mode 100644 index 0000000..e97f626 --- /dev/null +++ b/riscv/insns/sw_rl.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZALASR); +MMU.store(RS1, RS2); diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index af4f925..fac4186 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -81,6 +81,7 @@ typedef enum { EXT_SSCSRIND, EXT_SMCNTRPMF, EXT_ZCMOP, + EXT_ZALASR, NUM_ISA_EXTENSIONS } isa_extension_t; diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index ecf4fa0..f0c55aa 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1300,6 +1300,16 @@ riscv_insn_ext_zacas = \ amocas_d \ $(if $(HAVE_INT128),amocas_q) +riscv_insn_ext_zalasr = \ + lb_aq \ + lh_aq \ + lw_aq \ + ld_aq \ + sb_rl \ + sh_rl \ + sw_rl \ + sd_rl \ + riscv_insn_ext_zvbb = \ vandn_vv \ vandn_vx \ @@ -1384,6 +1394,7 @@ riscv_insn_list = \ $(riscv_insn_ext_q) \ $(riscv_insn_ext_q_zfa) \ $(riscv_insn_ext_zacas) \ + $(riscv_insn_ext_zalasr) \ $(riscv_insn_ext_zce) \ $(riscv_insn_ext_zfh) \ $(riscv_insn_ext_zfh_zfa) \ -- cgit v1.1 From 177ecae3656acc8d66d0c50687cd92fad169e8cd Mon Sep 17 00:00:00 2001 From: brs Date: Thu, 19 Oct 2023 10:55:40 -0500 Subject: Update to Zalasr encodings to require the aq/rl bits be set rather than assuming they are --- riscv/encoding.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 1a0f554..7ee3e3d 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (4f28129) + * https://github.com/riscv/riscv-opcodes (65c40e9) */ #ifndef RISCV_CSR_ENCODING_H @@ -1386,20 +1386,20 @@ #define MASK_KWMMUL_U 0xfe00707f #define MATCH_LB 0x3 #define MASK_LB 0x707f -#define MATCH_LB_AQ 0x3000002f -#define MASK_LB_AQ 0xf9f0707f +#define MATCH_LB_AQ 0x3400002f +#define MASK_LB_AQ 0xfdf0707f #define MATCH_LBU 0x4003 #define MASK_LBU 0x707f #define MATCH_LD 0x3003 #define MASK_LD 0x707f -#define MATCH_LD_AQ 0x3000302f -#define MASK_LD_AQ 0xf9f0707f +#define MATCH_LD_AQ 0x3400302f +#define MASK_LD_AQ 0xfdf0707f #define MATCH_LDU 0x7003 #define MASK_LDU 0x707f #define MATCH_LH 0x1003 #define MASK_LH 0x707f -#define MATCH_LH_AQ 0x3000102f -#define MASK_LH_AQ 0xf9f0707f +#define MATCH_LH_AQ 0x3400102f +#define MASK_LH_AQ 0xfdf0707f #define MATCH_LHU 0x5003 #define MASK_LHU 0x707f #define MATCH_LQ 0x300f @@ -1412,8 +1412,8 @@ #define MASK_LUI 0x7f #define MATCH_LW 0x2003 #define MASK_LW 0x707f -#define MATCH_LW_AQ 0x3000202f -#define MASK_LW_AQ 0xf9f0707f +#define MATCH_LW_AQ 0x3400202f +#define MASK_LW_AQ 0xfdf0707f #define MATCH_LWU 0x6003 #define MASK_LWU 0x707f #define MATCH_MADDR32 0xc4001077 @@ -1628,8 +1628,8 @@ #define MASK_RSUBW 0xfe00707f #define MATCH_SB 0x23 #define MASK_SB 0x707f -#define MATCH_SB_RL 0x3800002f -#define MASK_SB_RL 0xf8007fff +#define MATCH_SB_RL 0x3a00002f +#define MASK_SB_RL 0xfa007fff #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f #define MATCH_SC_W 0x1800202f @@ -1650,8 +1650,8 @@ #define MASK_SCMPLT8 0xfe00707f #define MATCH_SD 0x3023 #define MASK_SD 0x707f -#define MATCH_SD_RL 0x3800302f -#define MASK_SD_RL 0xf8007fff +#define MATCH_SD_RL 0x3a00302f +#define MASK_SD_RL 0xfa007fff #define MATCH_SEXT_B 0x60401013 #define MASK_SEXT_B 0xfff0707f #define MATCH_SEXT_H 0x60501013 @@ -1676,8 +1676,8 @@ #define MASK_SH3ADD 0xfe00707f #define MATCH_SH3ADD_UW 0x2000603b #define MASK_SH3ADD_UW 0xfe00707f -#define MATCH_SH_RL 0x3800102f -#define MASK_SH_RL 0xf8007fff +#define MATCH_SH_RL 0x3a00102f +#define MASK_SH_RL 0xfa007fff #define MATCH_SHA256SIG0 0x10201013 #define MASK_SHA256SIG0 0xfff0707f #define MATCH_SHA256SIG1 0x10301013 @@ -1984,8 +1984,8 @@ #define MASK_SUNPKD832 0xfff0707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f -#define MATCH_SW_RL 0x3800202f -#define MASK_SW_RL 0xf8007fff +#define MATCH_SW_RL 0x3a00202f +#define MASK_SW_RL 0xfa007fff #define MATCH_UCLIP16 0x85000077 #define MASK_UCLIP16 0xff00707f #define MATCH_UCLIP32 0xf4000077 -- cgit v1.1 From 37e00ffb6e9544bda894a16456955a9ef88c87fd Mon Sep 17 00:00:00 2001 From: brs Date: Thu, 19 Oct 2023 11:12:02 -0500 Subject: Update README on adding new instructions to point out that they need to be added to riscv.mk.in --- README.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e850b6e..2c5bba9 100644 --- a/README.md +++ b/README.md @@ -130,7 +130,10 @@ Adding an instruction to the simulator requires two steps: $ make install ``` - 3. Rebuild the simulator. + 3. Add the instruction to riscv/riscv.mk.in. Otherwise, the instruction + will not be included in the build and will be treated as an illegal instruction. + + 4. Rebuild the simulator. Interactive Debug Mode --------------------------- -- cgit v1.1