From f33da38e71994c819ff373bd24ab3a5bfaa8e4bd Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 14 Apr 2023 22:47:51 +0800
Subject: Add support for new instructions of Zvfbfmin extension

---
 riscv/insns/vfncvtbf16_f_f_w.h |  5 +++++
 riscv/insns/vfwcvtbf16_f_f_v.h |  5 +++++
 riscv/riscv.mk.in              |  5 +++++
 riscv/v_ext_macros.h           | 22 ++++++++++++++++++++++
 4 files changed, 37 insertions(+)
 create mode 100644 riscv/insns/vfncvtbf16_f_f_w.h
 create mode 100644 riscv/insns/vfwcvtbf16_f_f_v.h

diff --git a/riscv/insns/vfncvtbf16_f_f_w.h b/riscv/insns/vfncvtbf16_f_f_w.h
new file mode 100644
index 0000000..4708802
--- /dev/null
+++ b/riscv/insns/vfncvtbf16_f_f_w.h
@@ -0,0 +1,5 @@
+// vfncvtbf16.f.f.w vd, vs2, vm
+VI_VFP_NCVT_BF16_TO_FP(
+  { vd = f32_to_bf16(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)
diff --git a/riscv/insns/vfwcvtbf16_f_f_v.h b/riscv/insns/vfwcvtbf16_f_f_v.h
new file mode 100644
index 0000000..ee9a59c
--- /dev/null
+++ b/riscv/insns/vfwcvtbf16_f_f_v.h
@@ -0,0 +1,5 @@
+// vfwcvtbf16.f.f.v vd, vs2, vm
+VI_VFP_WCVT_FP_TO_BF16(
+  { vd = bf16_to_f32(vs2); },           // BODY16
+  { require_extension(EXT_ZVFBFMIN); }  // CHECK16
+)
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 19de2b8..aeffe36 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1361,8 +1361,13 @@ riscv_insn_ext_zfbfmin = \
 	fcvt_bf16_s \
 	fcvt_s_bf16 \
 
+riscv_insn_ext_zvfbfmin = \
+	vfncvtbf16_f_f_w \
+	vfwcvtbf16_f_f_v \
+
 riscv_insn_ext_bf16 = \
 	$(riscv_insn_ext_zfbfmin) \
+	$(riscv_insn_ext_zvfbfmin) \
 
 riscv_insn_list = \
 	$(riscv_insn_ext_a) \
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h
index 3fc0162..31328d5 100644
--- a/riscv/v_ext_macros.h
+++ b/riscv/v_ext_macros.h
@@ -1979,6 +1979,17 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
+#define VI_VFP_WCVT_FP_TO_BF16(BODY, CHECK) \
+  VI_CHECK_DSS(false); \
+  switch (P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(16, 32), CHECK, BODY); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_WCVT_INT_TO_FP(BODY8, BODY16, BODY32, \
                               CHECK8, CHECK16, CHECK32, \
                               sign) \
@@ -2029,6 +2040,17 @@ reg_t index[P.VU.vlmax]; \
       break; \
   }
 
+#define VI_VFP_NCVT_BF16_TO_FP(BODY, CHECK) \
+  VI_CHECK_SDS(false); \
+  switch (P.VU.vsew) { \
+    case e16: \
+      { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK, BODY); } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
+
 #define VI_VFP_NCVT_INT_TO_FP(BODY8, BODY16, BODY32, \
                               CHECK8, CHECK16, CHECK32, \
                               sign) \
-- 
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