From eace5599606034850e28eef63f1e00eaf8eb6d26 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 18 Feb 2017 03:03:10 -0800 Subject: Spike uarch needs TLB flush after SPTBR write --- riscv/encoding.h | 1 - riscv/processor.cc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index d205761..9a87807 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -19,7 +19,6 @@ #define MSTATUS_MPRV 0x00020000 #define MSTATUS_PUM 0x00040000 #define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000 diff --git a/riscv/processor.cc b/riscv/processor.cc index 1883757..ddef0e2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -362,6 +362,7 @@ void processor_t::set_csr(int which, reg_t val) return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); case CSR_SPTBR: { + mmu->flush_tlb(); if (max_xlen == 32) state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || -- cgit v1.1