From 7ed22f01fc8590582d75aa46adaf76409fc198f6 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Thu, 27 Apr 2023 13:19:11 -0700 Subject: Introduce interrupt_bit which I will reuse next --- riscv/processor.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 3c923ea..f9c1a66 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -866,7 +866,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc) reg_t vsdeleg, hsdeleg; reg_t bit = t.cause(); bool curr_virt = state.v; - bool interrupt = (bit & ((reg_t)1 << (max_xlen - 1))) != 0; + const reg_t interrupt_bit = (reg_t)1 << (max_xlen - 1); + bool interrupt = (bit & interrupt_bit) != 0; if (interrupt) { vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0; hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0; -- cgit v1.1 From 073510dbd46f53a71b09633a802fcd97ee38a3ac Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Thu, 27 Apr 2023 13:26:04 -0700 Subject: Introduce adjusted_cause which I will reuse next --- riscv/processor.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index f9c1a66..d02c6d5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -878,9 +878,10 @@ void processor_t::take_trap(trap_t& t, reg_t epc) } if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { // Handle the trap in VS-mode + const reg_t adjusted_cause = interrupt ? bit - 1 : bit; // VSSIP -> SSIP, etc reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; - state.vscause->write((interrupt) ? (t.cause() - 1) : t.cause()); + state.vscause->write(adjusted_cause | (interrupt ? interrupt_bit : 0)); state.vsepc->write(epc); state.vstval->write(t.get_tval()); -- cgit v1.1 From 69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Thu, 27 Apr 2023 13:26:40 -0700 Subject: Fix vectored VS-level interrupts They were going to the vector for cause 10 (VSEI) even though vscause had been correctly translated to 9 (SEI). Fixes #1340. --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index d02c6d5..9739ab7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -879,7 +879,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { // Handle the trap in VS-mode const reg_t adjusted_cause = interrupt ? bit - 1 : bit; // VSSIP -> SSIP, etc - reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; + reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * adjusted_cause : 0; state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; state.vscause->write(adjusted_cause | (interrupt ? interrupt_bit : 0)); state.vsepc->write(epc); -- cgit v1.1