From b1f2ae41a1e64f416fb5f5aa092352439ecefa83 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 19 Oct 2022 21:40:42 -0700 Subject: Template-ize stores --- riscv/debug_module.cc | 8 ++++---- riscv/insns/c_fsd.h | 2 +- riscv/insns/c_fsdsp.h | 2 +- riscv/insns/c_fsw.h | 4 ++-- riscv/insns/c_fswsp.h | 4 ++-- riscv/insns/c_sw.h | 2 +- riscv/insns/c_swsp.h | 2 +- riscv/insns/fsd.h | 2 +- riscv/insns/fsh.h | 2 +- riscv/insns/fsw.h | 2 +- riscv/insns/sb.h | 2 +- riscv/insns/sd.h | 2 +- riscv/insns/sh.h | 2 +- riscv/insns/sw.h | 2 +- riscv/mmu.h | 16 +++------------- riscv/sim.cc | 2 +- riscv/v_ext_macros.h | 14 +++++++------- 17 files changed, 30 insertions(+), 40 deletions(-) diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 341cd04..2f48dd2 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -340,13 +340,13 @@ void debug_module_t::sb_write() reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) { - sim->debug_mmu->store_uint8(address, sbdata[0]); + sim->debug_mmu->store(address, sbdata[0]); } else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) { - sim->debug_mmu->store_uint16(address, sbdata[0]); + sim->debug_mmu->store(address, sbdata[0]); } else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) { - sim->debug_mmu->store_uint32(address, sbdata[0]); + sim->debug_mmu->store(address, sbdata[0]); } else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) { - sim->debug_mmu->store_uint64(address, + sim->debug_mmu->store(address, (((uint64_t) sbdata[1]) << 32) | sbdata[0]); } else { sbcs.error = 3; diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h index 6f2c8f4..58c3bcf 100644 --- a/riscv/insns/c_fsd.h +++ b/riscv/insns/c_fsd.h @@ -1,4 +1,4 @@ require_extension('C'); require_extension('D'); require_fp; -MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); +MMU.store(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h index 27b9331..ebe7995 100644 --- a/riscv/insns/c_fsdsp.h +++ b/riscv/insns/c_fsdsp.h @@ -1,4 +1,4 @@ require_extension('C'); require_extension('D'); require_fp; -MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); +MMU.store(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index 7085822..381ab5e 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); + MMU.store(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); } else { // c.sd - MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); + MMU.store(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); } diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h index c5a003f..9ce408c 100644 --- a/riscv/insns/c_fswsp.h +++ b/riscv/insns/c_fswsp.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]); + MMU.store(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]); } else { // c.sdsp - MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); + MMU.store(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); } diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h index 3073e9d..43f397f 100644 --- a/riscv/insns/c_sw.h +++ b/riscv/insns/c_sw.h @@ -1,2 +1,2 @@ require_extension('C'); -MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S); +MMU.store(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S); diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h index b8995ab..a01e466 100644 --- a/riscv/insns/c_swsp.h +++ b/riscv/insns/c_swsp.h @@ -1,2 +1,2 @@ require_extension('C'); -MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2); +MMU.store(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2); diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h index 38c702b..babc9e5 100644 --- a/riscv/insns/fsd.h +++ b/riscv/insns/fsd.h @@ -1,3 +1,3 @@ require_extension('D'); require_fp; -MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v[0]); +MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h index 9eaae1e..dfd6bc5 100644 --- a/riscv/insns/fsh.h +++ b/riscv/insns/fsh.h @@ -1,3 +1,3 @@ require_extension(EXT_ZFHMIN); require_fp; -MMU.store_uint16(RS1 + insn.s_imm(), FRS2.v[0]); +MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h index 8af5184..887f03e 100644 --- a/riscv/insns/fsw.h +++ b/riscv/insns/fsw.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]); +MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h index 8729c2d..d9cc8f9 100644 --- a/riscv/insns/sb.h +++ b/riscv/insns/sb.h @@ -1 +1 @@ -MMU.store_uint8(RS1 + insn.s_imm(), RS2); +MMU.store(RS1 + insn.s_imm(), RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h index 664deb2..5c9dd4e 100644 --- a/riscv/insns/sd.h +++ b/riscv/insns/sd.h @@ -1,2 +1,2 @@ require_rv64; -MMU.store_uint64(RS1 + insn.s_imm(), RS2); +MMU.store(RS1 + insn.s_imm(), RS2); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h index 22aa3a8..8f780c3 100644 --- a/riscv/insns/sh.h +++ b/riscv/insns/sh.h @@ -1 +1 @@ -MMU.store_uint16(RS1 + insn.s_imm(), RS2); +MMU.store(RS1 + insn.s_imm(), RS2); diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h index aa5ead3..a9d7268 100644 --- a/riscv/insns/sw.h +++ b/riscv/insns/sw.h @@ -1 +1 @@ -MMU.store_uint32(RS1 + insn.s_imm(), RS2); +MMU.store(RS1 + insn.s_imm(), RS2); diff --git a/riscv/mmu.h b/riscv/mmu.h index 22edd6f..8a0e921 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -123,10 +123,6 @@ public: store(addr, val, RISCV_XLATE_VIRT); } - // template for functions that store an aligned value to memory - #define store_func(type, prefix, xlate_flags) \ - void ALWAYS_INLINE prefix##_##type(reg_t addr, type##_t val) { store(addr, val, xlate_flags); } - // AMO/Zicbom faults should be reported as store faults #define convert_load_traps_to_store_traps(BODY) \ try { \ @@ -159,8 +155,8 @@ public: if (unlikely(addr & (sizeof(float128_t)-1))) throw trap_store_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0); #endif - store_uint64(addr, val.v[0]); - store_uint64(addr + 8, val.v[1]); + store(addr, val.v[0]); + store(addr + 8, val.v[1]); } float128_t load_float128(reg_t addr) @@ -172,16 +168,10 @@ public: return (float128_t){load(addr), load(addr + 8)}; } - // store value to memory at aligned address - store_func(uint8, store, 0) - store_func(uint16, store, 0) - store_func(uint32, store, 0) - store_func(uint64, store, 0) - void cbo_zero(reg_t addr) { auto base = addr & ~(blocksz - 1); for (size_t offset = 0; offset < blocksz; offset += 1) - store_uint8(base + offset, 0); + store(base + offset, 0); } void clean_inval(reg_t addr, bool clean, bool inval) { diff --git a/riscv/sim.cc b/riscv/sim.cc index 240133d..71ac452 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -429,7 +429,7 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) assert(len == 8); target_endian data; memcpy(&data, src, sizeof data); - debug_mmu->store_uint64(taddr, debug_mmu->from_target(data)); + debug_mmu->store(taddr, debug_mmu->from_target(data)); } void sim_t::set_target_endianness(memif_endianness_t endianness) diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 82d5622..0984a80 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1238,7 +1238,7 @@ reg_t index[P.VU.vlmax]; \ P.VU.vstart->write(i); \ for (reg_t fn = 0; fn < nf; ++fn) { \ elt_width##_t val = P.VU.elt(vs3 + fn * emul, vreg_inx); \ - MMU.store_##elt_width( \ + MMU.store( \ baseAddr + (stride) + (offset) * sizeof(elt_width##_t), val); \ } \ } \ @@ -1260,19 +1260,19 @@ reg_t index[P.VU.vlmax]; \ for (reg_t fn = 0; fn < nf; ++fn) { \ switch (P.VU.vsew) { \ case e8: \ - MMU.store_uint8(baseAddr + index[i] + fn * 1, \ + MMU.store(baseAddr + index[i] + fn * 1, \ P.VU.elt(vs3 + fn * flmul, vreg_inx)); \ break; \ case e16: \ - MMU.store_uint16(baseAddr + index[i] + fn * 2, \ + MMU.store(baseAddr + index[i] + fn * 2, \ P.VU.elt(vs3 + fn * flmul, vreg_inx)); \ break; \ case e32: \ - MMU.store_uint32(baseAddr + index[i] + fn * 4, \ + MMU.store(baseAddr + index[i] + fn * 4, \ P.VU.elt(vs3 + fn * flmul, vreg_inx)); \ break; \ default: \ - MMU.store_uint64(baseAddr + index[i] + fn * 8, \ + MMU.store(baseAddr + index[i] + fn * 8, \ P.VU.elt(vs3 + fn * flmul, vreg_inx)); \ break; \ } \ @@ -1359,7 +1359,7 @@ reg_t index[P.VU.vlmax]; \ if (off) { \ for (reg_t pos = off; pos < P.VU.vlenb; ++pos) { \ auto val = P.VU.elt(vs3 + i, pos); \ - MMU.store_uint8(baseAddr + P.VU.vstart->read(), val); \ + MMU.store(baseAddr + P.VU.vstart->read(), val); \ P.VU.vstart->write(P.VU.vstart->read() + 1); \ } \ i++; \ @@ -1367,7 +1367,7 @@ reg_t index[P.VU.vlmax]; \ for (; i < len; ++i) { \ for (reg_t pos = 0; pos < P.VU.vlenb; ++pos) { \ auto val = P.VU.elt(vs3 + i, pos); \ - MMU.store_uint8(baseAddr + P.VU.vstart->read(), val); \ + MMU.store(baseAddr + P.VU.vstart->read(), val); \ P.VU.vstart->write(P.VU.vstart->read() + 1); \ } \ } \ -- cgit v1.1