From a82ef286216bad81db9477c1c8bc13bb48d6561c Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 14 Oct 2022 11:53:02 -0700
Subject: Add command to display privilege level in interactive mode

---
 riscv/interactive.cc | 12 ++++++++++++
 riscv/processor.cc   | 18 ++++++++++++++++++
 riscv/processor.h    |  1 +
 riscv/sim.h          |  1 +
 4 files changed, 32 insertions(+)

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index cf95bf6..e64e321 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -313,6 +313,7 @@ void sim_t::interactive()
   funcs["fregs"] = &sim_t::interactive_fregs;
   funcs["fregd"] = &sim_t::interactive_fregd;
   funcs["pc"] = &sim_t::interactive_pc;
+  funcs["priv"] = &sim_t::interactive_priv;
   funcs["mem"] = &sim_t::interactive_mem;
   funcs["str"] = &sim_t::interactive_str;
   funcs["mtime"] = &sim_t::interactive_mtime;
@@ -396,6 +397,7 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri
     "fregd <core> <reg>              # Display double precision <reg> in <core>\n"
     "vreg <core> [reg]               # Display vector [reg] (all if omitted) in <core>\n"
     "pc <core>                       # Show current PC in <core>\n"
+    "priv <core>                     # Show current privilege level in <core>\n"
     "mem [core] <hex addr>           # Show contents of virtual memory <hex addr> in [core] (physical memory <hex addr> if omitted)\n"
     "str [core] <hex addr>           # Show NUL-terminated C string at virtual address <hex addr> in [core] (physical address <hex addr> if omitted)\n"
     "dump                            # Dump physical memory to binary files\n"
@@ -470,6 +472,16 @@ void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string
       << zext(get_pc(args), max_xlen) << std::endl;
 }
 
+void sim_t::interactive_priv(const std::string& cmd, const std::vector<std::string>& args)
+{
+  if (args.size() != 1)
+    throw trap_interactive();
+
+  processor_t *p = get_core(args[0]);
+  std::ostream out(sout_.rdbuf());
+  out << p->get_privilege_string() << std::endl;
+}
+
 reg_t sim_t::get_reg(const std::vector<std::string>& args)
 {
   if (args.size() != 2)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 217d49d..d790d3f 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -755,6 +755,24 @@ void processor_t::set_privilege(reg_t prv)
   state.prv = legalize_privilege(prv);
 }
 
+const char* processor_t::get_privilege_string()
+{
+  if (state.v) {
+    switch (state.prv) {
+    case 0x0: return "VU";
+    case 0x1: return "VS";
+    }
+  } else {
+    switch (state.prv) {
+    case 0x0: return "U";
+    case 0x1: return "S";
+    case 0x3: return "M";
+    }
+  }
+  fprintf(stderr, "Invalid prv=%lx v=%x\n", state.prv, state.v);
+  abort();
+}
+
 void processor_t::set_virt(bool virt)
 {
   reg_t tmp, mask;
diff --git a/riscv/processor.h b/riscv/processor.h
index 8194046..7d5552b 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -299,6 +299,7 @@ public:
   reg_t legalize_privilege(reg_t);
   void set_privilege(reg_t);
   void set_virt(bool);
+  const char* get_privilege_string();
   void update_histogram(reg_t pc);
   const disassembler_t* get_disassembler() { return disassembler; }
 
diff --git a/riscv/sim.h b/riscv/sim.h
index 7816b87..a2ffeee 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -136,6 +136,7 @@ private:
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_priv(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_dumpmems(const std::string& cmd, const std::vector<std::string>& args);
-- 
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