From 61d54d0e07d96a2b6bb9e4cb9b8c5ae9260be3de Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 15 Nov 2023 16:42:07 -0800
Subject: tmp

---
 riscv/mmu.cc       |  3 ++-
 riscv/mmu.h        | 12 ++++++------
 riscv/processor.cc |  3 +++
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 285ef6d..0b97e9a 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -327,7 +327,8 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_
 
   if ((check_triggers_fetch && type == FETCH) ||
       (check_triggers_load && type == LOAD) ||
-      (check_triggers_store && type == STORE))
+      (check_triggers_store && type == STORE) ||
+      (proc && proc->get_log_commits_enabled()))
     expected_tag |= TLB_CHECK_TRIGGERS;
 
   if (pmp_homogeneous(paddr & ~reg_t(PGSIZE - 1), PGSIZE)) {
diff --git a/riscv/mmu.h b/riscv/mmu.h
index ce50527..b1a0e3b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -104,10 +104,10 @@ public:
       res = *(target_endian<T>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr);
     } else {
       load_slow_path(addr, sizeof(T), (uint8_t*)&res, xlate_flags);
-    }
 
-    if (unlikely(proc && proc->get_log_commits_enabled()))
-      proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, sizeof(T)));
+      if (unlikely(proc && proc->get_log_commits_enabled()))
+        proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, sizeof(T)));
+    }
 
     return from_target(res);
   }
@@ -147,10 +147,10 @@ public:
     } else {
       target_endian<T> target_val = to_target(val);
       store_slow_path(addr, sizeof(T), (const uint8_t*)&target_val, xlate_flags, true, false);
-    }
 
-    if (unlikely(proc && proc->get_log_commits_enabled()))
-      proc->state.log_mem_write.push_back(std::make_tuple(addr, val, sizeof(T)));
+      if (unlikely(proc && proc->get_log_commits_enabled()))
+        proc->state.log_mem_write.push_back(std::make_tuple(addr, val, sizeof(T)));
+    }
   }
 
   template<typename T>
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0ac6e67..469da1e 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -611,6 +611,9 @@ void processor_t::set_histogram(bool value)
 void processor_t::enable_log_commits()
 {
   log_commits_enabled = true;
+
+  // commit logging occurs on the TLB-miss path
+  mmu->flush_tlb();
 }
 
 void processor_t::reset()
-- 
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