From 5daafcde73f448a702356e049911b5677a1811c2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 22 Jul 2016 14:05:06 -0700 Subject: Set U bit in misa register --- riscv/processor.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 8c89e3f..8c267f4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -84,6 +84,7 @@ void processor_t::parse_isa_string(const char* str) isa_string = "rv" + std::to_string(max_xlen) + p; isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode + isa |= 1L << ('u' - 'a'); // advertise support for user mode while (*p) { isa |= 1L << (*p - 'a'); -- cgit v1.1