From 07c2e2bfcbeae79f5bda72146d8d5652a40f8861 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 14 Aug 2023 12:44:57 -0500 Subject: rename *envcfg.HADE to *envcfg.ADUE --- riscv/csrs.h | 2 +- riscv/encoding.h | 18 +++++++++--------- riscv/mmu.cc | 4 ++-- riscv/processor.cc | 4 ++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/riscv/csrs.h b/riscv/csrs.h index 5ca7e15..efa7f10 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -479,7 +479,7 @@ class henvcfg_csr_t final: public envcfg_csr_t { henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg); reg_t read() const noexcept override { - return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_HADE)) & masked_csr_t::read(); + return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_ADUE)) & masked_csr_t::read(); } virtual void verify_permissions(insn_t insn, bool write) const override; diff --git a/riscv/encoding.h b/riscv/encoding.h index f1defd4..a7e2d94 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (6790b30) + * https://github.com/riscv/riscv-opcodes (d752f19) */ #ifndef RISCV_CSR_ENCODING_H @@ -160,11 +160,11 @@ #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 -#define MENVCFG_HADE 0x2000000000000000 +#define MENVCFG_ADUE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 -#define MENVCFGH_HADE 0x20000000 +#define MENVCFGH_ADUE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 #define MENVCFGH_STCE 0x80000000 @@ -198,11 +198,11 @@ #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 #define HENVCFG_CBZE 0x00000080 -#define HENVCFG_HADE 0x2000000000000000 +#define HENVCFG_ADUE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 #define HENVCFG_STCE 0x8000000000000000 -#define HENVCFGH_HADE 0x20000000 +#define HENVCFGH_ADUE 0x20000000 #define HENVCFGH_PBMTE 0x40000000 #define HENVCFGH_STCE 0x80000000 @@ -1004,10 +1004,10 @@ #define MASK_FMVH_X_D 0xfff0707f #define MATCH_FMVH_X_Q 0xe6100053 #define MASK_FMVH_X_Q 0xfff0707f -#define MATCH_FMVP_D_X 0xb2100053 -#define MASK_FMVP_D_X 0xfff0707f -#define MATCH_FMVP_Q_X 0xb6100053 -#define MASK_FMVP_Q_X 0xfff0707f +#define MATCH_FMVP_D_X 0xb2000053 +#define MASK_FMVP_D_X 0xfe00707f +#define MATCH_FMVP_Q_X 0xb6000053 +#define MASK_FMVP_Q_X 0xfe00707f #define MATCH_FNMADD_D 0x200004f #define MASK_FNMADD_D 0x600007f #define MATCH_FNMADD_H 0x400004f diff --git a/riscv/mmu.cc b/riscv/mmu.cc index f6d23a3..285ef6d 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -413,7 +413,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty reg_t pte = pte_load(pte_paddr, gva, virt, trap_type, vm.ptesize); reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT; bool pbmte = proc->get_state()->menvcfg->read() & MENVCFG_PBMTE; - bool hade = proc->get_state()->menvcfg->read() & MENVCFG_HADE; + bool hade = proc->get_state()->menvcfg->read() & MENVCFG_ADUE; if (pte & PTE_RSVD) { break; @@ -507,7 +507,7 @@ reg_t mmu_t::walk(mem_access_info_t access_info) reg_t pte = pte_load(pte_paddr, addr, virt, type, vm.ptesize); reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT; bool pbmte = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_PBMTE) : (proc->get_state()->menvcfg->read() & MENVCFG_PBMTE); - bool hade = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_HADE) : (proc->get_state()->menvcfg->read() & MENVCFG_HADE); + bool hade = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_ADUE) : (proc->get_state()->menvcfg->read() & MENVCFG_ADUE); if (pte & PTE_RSVD) { break; diff --git a/riscv/processor.cc b/riscv/processor.cc index 0704d8c..22e6542 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -450,7 +450,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) if (proc->extension_enabled_const('U')) { const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) | (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) | - (proc->extension_enabled(EXT_SVADU) ? MENVCFG_HADE: 0) | + (proc->extension_enabled(EXT_SVADU) ? MENVCFG_ADUE: 0) | (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) | (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0); const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0); @@ -466,7 +466,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) csrmap[CSR_SENVCFG] = senvcfg = std::make_shared(proc, CSR_SENVCFG, senvcfg_mask, 0); const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) | (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) | - (proc->extension_enabled(EXT_SVADU) ? HENVCFG_HADE: 0) | + (proc->extension_enabled(EXT_SVADU) ? HENVCFG_ADUE: 0) | (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) | (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0); const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0); -- cgit v1.1