From 055624200a34bcc8d4c7acde040466f7d2001637 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 12 Jun 2024 18:39:59 -0700
Subject: Fix a few compile warnings

---
 riscv/debug_module.h | 32 ++++++++++++++++----------------
 riscv/triggers.cc    |  2 +-
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index bca29b2..3771489 100644
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -11,7 +11,7 @@ class simif_t;
 class bus_t;
 class processor_t;
 
-typedef struct {
+struct debug_module_config_t {
   // Size of program_buffer in 32-bit words, as exposed to the rest of the
   // world.
   unsigned progbufsize = 2;
@@ -23,9 +23,9 @@ typedef struct {
   bool support_abstract_fpr_access = true;
   bool support_haltgroups = true;
   bool support_impebreak = true;
-} debug_module_config_t;
+};
 
-typedef struct {
+struct dmcontrol_t {
   bool haltreq;
   bool resumereq;
   bool hasel;
@@ -33,9 +33,9 @@ typedef struct {
   bool hartreset;
   bool dmactive;
   bool ndmreset;
-} dmcontrol_t;
+};
 
-typedef struct {
+struct dmstatus_t {
   bool impebreak;
   bool allhavereset;
   bool anyhavereset;
@@ -53,30 +53,30 @@ typedef struct {
   bool authbusy;
   bool cfgstrvalid;
   unsigned version;
-} dmstatus_t;
+};
 
-typedef enum cmderr {
+enum cmderr_t {
   CMDERR_NONE = 0,
   CMDERR_BUSY = 1,
   CMDERR_NOTSUP = 2,
   CMDERR_EXCEPTION = 3,
   CMDERR_HALTRESUME = 4,
   CMDERR_OTHER = 7
-} cmderr_t;
+};
 
-typedef struct {
+struct abstractcs_t {
   bool busy;
   unsigned datacount;
   unsigned progbufsize;
   cmderr_t cmderr;
-} abstractcs_t;
+};
 
-typedef struct {
+struct abstractauto_t {
   unsigned autoexecprogbuf;
   unsigned autoexecdata;
-} abstractauto_t;
+};
 
-typedef struct {
+struct sbcs_t {
   unsigned version;
   bool readonaddr;
   unsigned sbaccess;
@@ -90,14 +90,14 @@ typedef struct {
   bool access16;
   bool access8;
   bool sbbusyerror;
-} sbcs_t;
+};
 
-typedef struct {
+struct hart_debug_state_t {
   bool halted;
   bool resumeack;
   bool havereset;
   uint8_t haltgroup;
-} hart_debug_state_t;
+};
 
 class debug_module_t : public abstract_device_t
 {
diff --git a/riscv/triggers.cc b/riscv/triggers.cc
index aa258bd..de3da40 100644
--- a/riscv/triggers.cc
+++ b/riscv/triggers.cc
@@ -83,7 +83,7 @@ bool trigger_t::textra_match(processor_t * const proc) const noexcept
   if (sselect == SSELECT_SCONTEXT) {
     reg_t mask = (reg_t(1) << ((xlen == 32) ? CSR_TEXTRA32_SVALUE_LENGTH : CSR_TEXTRA64_SVALUE_LENGTH)) - 1;
     assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH);
-    for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++)
+    for (unsigned i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++)
       if (sbytemask & (1 << i))
         mask &= ~(reg_t(0xff) << (i * 8));
     if ((state->scontext->read() & mask) != (svalue & mask))
-- 
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