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-rw-r--r--riscv/csrs.cc13
-rw-r--r--riscv/csrs.h5
-rw-r--r--riscv/processor.cc2
-rw-r--r--riscv/processor.h2
-rw-r--r--riscv/triggers.h1
5 files changed, 8 insertions, 15 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index c448e04..db07ce4 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -1039,24 +1039,19 @@ bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept {
}
-tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr, const size_t count):
- csr_t(proc, addr),
- vals(count, 0) {
+tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr):
+ csr_t(proc, addr) {
}
reg_t tdata2_csr_t::read() const noexcept {
- return read(state->tselect->read());
-}
-
-reg_t tdata2_csr_t::read(const size_t idx) const noexcept {
- return vals[idx];
+ return proc->TM.triggers[state->tselect->read()]->tdata2;
}
bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept {
if (proc->TM.triggers[state->tselect->read()]->dmode && !state->debug_mode) {
return false;
}
- vals[state->tselect->read()] = val;
+ proc->TM.triggers[state->tselect->read()]->tdata2 = val;
return true;
}
diff --git a/riscv/csrs.h b/riscv/csrs.h
index 0cbe8c5..c83283e 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -574,13 +574,10 @@ class tdata1_csr_t: public csr_t {
class tdata2_csr_t: public csr_t {
public:
- tdata2_csr_t(processor_t* const proc, const reg_t addr, const size_t count);
+ tdata2_csr_t(processor_t* const proc, const reg_t addr);
virtual reg_t read() const noexcept override;
- reg_t read(const size_t idx) const noexcept;
protected:
virtual bool unlogged_write(const reg_t val) noexcept override;
- private:
- std::vector<reg_t> vals;
};
// For CSRs that are only writable from debug mode
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8f5fc87..5d0e5bc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -351,7 +351,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
csrmap[CSR_TSELECT] = tselect = std::make_shared<tselect_csr_t>(proc, CSR_TSELECT);
csrmap[CSR_TDATA1] = std::make_shared<tdata1_csr_t>(proc, CSR_TDATA1);
- csrmap[CSR_TDATA2] = tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2, num_triggers);
+ csrmap[CSR_TDATA2] = tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2);
csrmap[CSR_TDATA3] = std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0);
debug_mode = false;
single_step = STEP_NONE;
diff --git a/riscv/processor.h b/riscv/processor.h
index ba352fc..baa2934 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -352,7 +352,7 @@ public:
value &= 0xffffffff;
}
- auto tdata2 = state.tdata2->read(i);
+ auto tdata2 = TM.triggers[i]->tdata2;
switch (TM.triggers[i]->match) {
case triggers::mcontrol_t::MATCH_EQUAL:
if (value != tdata2)
diff --git a/riscv/triggers.h b/riscv/triggers.h
index b05e415..bcafcdd 100644
--- a/riscv/triggers.h
+++ b/riscv/triggers.h
@@ -58,6 +58,7 @@ public:
bool execute;
bool store;
bool load;
+ reg_t tdata2;
};
class module_t {