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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 08:22:20 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 08:22:48 +0800 |
commit | 396910b869a66cba55b7c09100b2080137ce39fe (patch) | |
tree | 2ec90189e8835b74c80bd587e28199594eac95f7 /riscv | |
parent | 6f0fb68d5879999c31a8c9bb274a4f7f31bd89f1 (diff) | |
download | riscv-isa-sim-396910b869a66cba55b7c09100b2080137ce39fe.zip riscv-isa-sim-396910b869a66cba55b7c09100b2080137ce39fe.tar.gz riscv-isa-sim-396910b869a66cba55b7c09100b2080137ce39fe.tar.bz2 |
Rename parameters for VI_VFP_NCVT* macros to be consistent with the
comments in vfncvt*.h
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/v_ext_macros.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index ea15fa2..0954d22 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -2014,50 +2014,50 @@ reg_t index[P.VU.vlmax]; \ break; \ } -#define VI_VFP_NCVT_FP_TO_FP(BODY16, BODY32, \ - CHECK16, CHECK32) \ +#define VI_VFP_NCVT_FP_TO_FP(BODY32, BODY64, \ + CHECK32, CHECK64) \ VI_CHECK_SDS(false); \ switch (P.VU.vsew) { \ case e16: \ - { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK16, BODY16); } \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK32, BODY32); } \ break; \ case e32: \ - { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(64, 32), CHECK32, BODY32); } \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(64, 32), CHECK64, BODY64); } \ break; \ default: \ require(0); \ break; \ } -#define VI_VFP_NCVT_INT_TO_FP(BODY16, BODY32, \ - CHECK16, CHECK32, \ +#define VI_VFP_NCVT_INT_TO_FP(BODY32, BODY64, \ + CHECK32, CHECK64, \ sign) \ VI_CHECK_SDS(false); \ switch (P.VU.vsew) { \ case e16: \ - { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 16, sign), CHECK16, BODY16); } \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 16, sign), CHECK32, BODY32); } \ break; \ case e32: \ - { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 32, sign), CHECK32, BODY32); } \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 32, sign), CHECK64, BODY64); } \ break; \ default: \ require(0); \ break; \ } -#define VI_VFP_NCVT_FP_TO_INT(BODY8, BODY16, BODY32, \ - CHECK8, CHECK16, CHECK32, \ +#define VI_VFP_NCVT_FP_TO_INT(BODY16, BODY32, BODY64, \ + CHECK16, CHECK32, CHECK64, \ sign) \ VI_CHECK_SDS(false); \ switch (P.VU.vsew) { \ case e8: \ - { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 8, sign), CHECK8, BODY8); } \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 8, sign), CHECK16, BODY16); } \ break; \ case e16: \ - { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 16, sign), CHECK16, BODY16); } \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 16, sign), CHECK32, BODY32); } \ break; \ case e32: \ - { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 32, sign), CHECK32, BODY32); } \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 32, sign), CHECK64, BODY64); } \ break; \ default: \ require(0); \ |