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| author | Tim Newsome <tim@sifive.com> | 2017-02-08 19:47:57 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-08 19:47:57 -0800 |
| commit | 48458198728a955c28428d83bfa31866be29c647 (patch) | |
| tree | 51164f5421c5a3133d03d0bc7bbc952c26941e2e /riscv/jtag_dtm.h | |
| parent | 94277648d5a0bb0e8283bbb33e25f6faab11c0d6 (diff) | |
| download | riscv-isa-sim-48458198728a955c28428d83bfa31866be29c647.zip riscv-isa-sim-48458198728a955c28428d83bfa31866be29c647.tar.gz riscv-isa-sim-48458198728a955c28428d83bfa31866be29c647.tar.bz2 | |
Serve up a correct dmcontrol register.
Diffstat (limited to 'riscv/jtag_dtm.h')
| -rw-r--r-- | riscv/jtag_dtm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h index 2bb4549..6d89c04 100644 --- a/riscv/jtag_dtm.h +++ b/riscv/jtag_dtm.h @@ -48,7 +48,7 @@ class jtag_dtm_t // constructor. const unsigned abits = 6; uint32_t dtmcontrol; - uint32_t dbus; + uint64_t dbus; jtag_state_t state; |