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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-16 10:51:12 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 14:12:53 +0800 |
| commit | b3ef6f76635436c7e9a7edc2a779060ca6c8be1f (patch) | |
| tree | 3e144f3f3cdea6cd0ffcc9a808d4c4313c6833f0 /riscv/insns | |
| parent | 383dbd3822042cdeb00c11597838bc1078271a22 (diff) | |
| download | riscv-isa-sim-b3ef6f76635436c7e9a7edc2a779060ca6c8be1f.zip riscv-isa-sim-b3ef6f76635436c7e9a7edc2a779060ca6c8be1f.tar.gz riscv-isa-sim-b3ef6f76635436c7e9a7edc2a779060ca6c8be1f.tar.bz2 | |
Remove redundant RVE related check in cm.mva01s and cm.mvsa01
r1s/r2s > 16 when r1sc/r1sc >2. This will also trigger illegal
instruction exception by CHECK_REG if RVE is enabled
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/cm_mva01s.h | 3 | ||||
| -rw-r--r-- | riscv/insns/cm_mvsa01.h | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/riscv/insns/cm_mva01s.h b/riscv/insns/cm_mva01s.h index 6212a8e..6504cae 100644 --- a/riscv/insns/cm_mva01s.h +++ b/riscv/insns/cm_mva01s.h @@ -1,6 +1,3 @@ require_extension(EXT_ZCMP); -if (p->extension_enabled('E')) { - require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); -} WRITE_REG(X_A0, READ_REG(RVC_R1S)); WRITE_REG(X_A1, READ_REG(RVC_R2S)); diff --git a/riscv/insns/cm_mvsa01.h b/riscv/insns/cm_mvsa01.h index 7288fbd..2214897 100644 --- a/riscv/insns/cm_mvsa01.h +++ b/riscv/insns/cm_mvsa01.h @@ -1,7 +1,4 @@ require_extension(EXT_ZCMP); -if (p->extension_enabled('E')) { - require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); -} require(insn.rvc_r1sc() != insn.rvc_r2sc()); WRITE_REG(RVC_R1S, READ_REG(X_A0)); WRITE_REG(RVC_R2S, READ_REG(X_A1)); |