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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:44:31 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-29 09:01:21 +0800 |
commit | 40dce7899b7a42d06413071c542606d4c0249174 (patch) | |
tree | aeb7244e93f1080a001d1ab881f4352844f387a0 /riscv/insns/fcvt_bf16_s.h | |
parent | c12d0782173ba00531bd48f653238d81cb9c3484 (diff) | |
download | riscv-isa-sim-40dce7899b7a42d06413071c542606d4c0249174.zip riscv-isa-sim-40dce7899b7a42d06413071c542606d4c0249174.tar.gz riscv-isa-sim-40dce7899b7a42d06413071c542606d4c0249174.tar.bz2 |
Add support for new instructions of Zfbfmin extension
Diffstat (limited to 'riscv/insns/fcvt_bf16_s.h')
-rw-r--r-- | riscv/insns/fcvt_bf16_s.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/insns/fcvt_bf16_s.h b/riscv/insns/fcvt_bf16_s.h new file mode 100644 index 0000000..d625df8 --- /dev/null +++ b/riscv/insns/fcvt_bf16_s.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZFBFMIN); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_BF(f32_to_bf16(FRS1_F)); +set_fp_exceptions; |