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author | Andrew Waterman <andrew@sifive.com> | 2021-07-28 17:11:06 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2021-07-28 17:11:06 -0700 |
commit | 25eb657276e0a6158339cccffdbb72c52d3f6dd8 (patch) | |
tree | 8d8b0e9890f4c6dd56c4e5a3cb098c7a338fc79e /riscv/execute.cc | |
parent | c8e510ec65e401832a1a3d8493a20b6b6705f957 (diff) | |
download | riscv-isa-sim-25eb657276e0a6158339cccffdbb72c52d3f6dd8.zip riscv-isa-sim-25eb657276e0a6158339cccffdbb72c52d3f6dd8.tar.gz riscv-isa-sim-25eb657276e0a6158339cccffdbb72c52d3f6dd8.tar.bz2 |
Inline execute_insn
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 6b53cf4..53f956c 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -170,7 +170,7 @@ inline void processor_t::update_histogram(reg_t pc) // This is expected to be inlined by the compiler so each use of execute_insn // includes a duplicated body of the function to get separate fetch.func // function calls. -static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) +static inline reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { commit_log_reset(p); commit_log_stash_privilege(p); |