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| author | Andrew Waterman <andrew@sifive.com> | 2024-09-26 18:19:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-26 18:19:36 -0700 |
| commit | 00cf1eb2a809369f0556ca143229009b675f5356 (patch) | |
| tree | c92859a716efd30db794c1818b7c06817395f162 /riscv/execute.cc | |
| parent | 666da337f821f802c5cc40458e85e4de2dc4df21 (diff) | |
| parent | 5c814c71340118f1d6259acf4a876abfe7344d9c (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
refactor: Remove dcsr::halt variable
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 5b8e523..1fa6111 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -216,8 +216,8 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0); } else if (halt_request == HR_GROUP) { enter_debug_mode(DCSR_CAUSE_GROUP, 0); - } else if (state.dcsr->halt) { - state.dcsr->halt = false; + } else if (halt_on_reset) { + halt_on_reset = false; enter_debug_mode(DCSR_CAUSE_HALT, 0); } } |