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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-31 20:39:47 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:35 +0800 |
commit | 793ffe508a5b81ce27f1baf2c5afb0b58a4236c6 (patch) | |
tree | c63cc0806775e5ced759ab202d187da8aa1a64c3 /riscv/debug_module.h | |
parent | db24e31569cab07f7d91c4f417aca12fab4fd018 (diff) | |
download | riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.zip riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.tar.gz riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.tar.bz2 |
Fix code indentation in processor.cc, interactive.cc, debug_module.h/cc
execute.cc, entropy_source.h and v_ext_macros.h
Diffstat (limited to 'riscv/debug_module.h')
-rw-r--r-- | riscv/debug_module.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/riscv/debug_module.h b/riscv/debug_module.h index d79ce7d..8230557 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -11,16 +11,16 @@ class sim_t; class bus_t; typedef struct { - // Size of program_buffer in 32-bit words, as exposed to the rest of the - // world. - unsigned progbufsize; - unsigned max_sba_data_width; - bool require_authentication; - unsigned abstract_rti; - bool support_hasel; - bool support_abstract_csr_access; - bool support_haltgroups; - bool support_impebreak; + // Size of program_buffer in 32-bit words, as exposed to the rest of the + // world. + unsigned progbufsize; + unsigned max_sba_data_width; + bool require_authentication; + unsigned abstract_rti; + bool support_hasel; + bool support_abstract_csr_access; + bool support_haltgroups; + bool support_impebreak; } debug_module_config_t; typedef struct { @@ -54,12 +54,12 @@ typedef struct { } dmstatus_t; typedef enum cmderr { - CMDERR_NONE = 0, - CMDERR_BUSY = 1, - CMDERR_NOTSUP = 2, - CMDERR_EXCEPTION = 3, - CMDERR_HALTRESUME = 4, - CMDERR_OTHER = 7 + CMDERR_NONE = 0, + CMDERR_BUSY = 1, + CMDERR_NOTSUP = 2, + CMDERR_EXCEPTION = 3, + CMDERR_HALTRESUME = 4, + CMDERR_OTHER = 7 } cmderr_t; typedef struct { |