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author | Andrew Waterman <andrew@sifive.com> | 2023-05-24 13:51:34 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-05-25 14:35:42 -0700 |
commit | d99efb545cca366a159dc1dedcbbd08fa2b3b8cf (patch) | |
tree | 56933e75e6963c14080a179315b48ac0ca6895e4 /riscv/csrs.cc | |
parent | e910707051c4e10889f58229443bf9d41652ed7b (diff) | |
download | riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.zip riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.tar.gz riscv-isa-sim-d99efb545cca366a159dc1dedcbbd08fa2b3b8cf.tar.bz2 |
Implement dcsr.v and make DRET use it
Resolves #1365
Diffstat (limited to 'riscv/csrs.cc')
-rw-r--r-- | riscv/csrs.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 9a165eb..95b5e22 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -13,6 +13,8 @@ #include "trap.h" // For require(): #include "insn_macros.h" +// For CSR_DCSR_V: +#include "debug_defines.h" // STATE macro used by require_privilege() macro: #undef STATE @@ -1234,6 +1236,7 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr): ebreaks(false), ebreaku(false), halt(false), + v(false), cause(0) { } @@ -1255,6 +1258,7 @@ reg_t dcsr_csr_t::read() const noexcept { result = set_field(result, DCSR_CAUSE, cause); result = set_field(result, DCSR_STEP, step); result = set_field(result, DCSR_PRV, prv); + result = set_field(result, CSR_DCSR_V, v); return result; } @@ -1267,12 +1271,14 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept { ebreaks = get_field(val, DCSR_EBREAKS); ebreaku = get_field(val, DCSR_EBREAKU); halt = get_field(val, DCSR_HALT); + v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false; return true; } -void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv) noexcept { +void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv, bool v) noexcept { this->cause = cause; this->prv = prv; + this->v = v; log_write(); } |