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author | Rupert Swarbrick <rswarbrick@lowrisc.org> | 2022-04-11 19:52:27 +0100 |
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committer | GitHub <noreply@github.com> | 2022-04-11 11:52:27 -0700 |
commit | 168b4ea6a568741e88156ed8f96b5df2765d9df7 (patch) | |
tree | 89cfee274199fd22294860f07972118dabf99f02 /riscv/cfg.h | |
parent | 7dc9283f31680a32110ad7f7296bde195c86399e (diff) | |
download | riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.zip riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.tar.gz riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.tar.bz2 |
Split mem layout computation in spike.cc (#957)
The motivation here is mostly to enable a refactoring where the memory
layout (sans allocated memory) gets passed to DTS/DTB code before we
ever allocate anything.
But it turns out to make merge_overlapping_memory_regions a bit
simpler, which is an added bonus.
Diffstat (limited to 'riscv/cfg.h')
-rw-r--r-- | riscv/cfg.h | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/riscv/cfg.h b/riscv/cfg.h index f0dea9f..e844738 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -3,6 +3,8 @@ #define _RISCV_CFG_H #include "decode.h" +#include "mmu.h" +#include <cassert> template <typename T> class cfg_arg_t { @@ -25,17 +27,41 @@ private: bool was_set; }; +// Configuration that describes a memory region +class mem_cfg_t +{ +public: + mem_cfg_t(reg_t base, reg_t size) + : base(base), size(size) + { + // The truth of these assertions should be ensured by whatever is creating + // the regions in the first place, but we have them here to make sure that + // we can't end up describing memory regions that don't make sense. They + // ask that the page size is a multiple of the minimum page size, that the + // page is aligned to the minimum page size, that the page is non-empty and + // that the top address is still representable in a reg_t. + assert((size % PGSIZE == 0) && + (base % PGSIZE == 0) && + (base + size > base)); + } + + reg_t base; + reg_t size; +}; + class cfg_t { public: cfg_t(std::pair<reg_t, reg_t> default_initrd_bounds, const char *default_bootargs, size_t default_nprocs, - const char *default_isa, const char *default_priv) + const char *default_isa, const char *default_priv, + const std::vector<mem_cfg_t> &default_mem_layout) : initrd_bounds(default_initrd_bounds), bootargs(default_bootargs), nprocs(default_nprocs), isa(default_isa), - priv(default_priv) + priv(default_priv), + mem_layout(default_mem_layout) {} cfg_arg_t<std::pair<reg_t, reg_t>> initrd_bounds; @@ -43,6 +69,7 @@ public: cfg_arg_t<size_t> nprocs; cfg_arg_t<const char *> isa; cfg_arg_t<const char *> priv; + cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; }; #endif |