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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2022-07-12 06:13:10 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-11 15:13:10 -0700 |
| commit | d920cdeeb47056e6976198384cd31f6e2e7b97da (patch) | |
| tree | abd2167ef6985e8c6d3f6154968754205cb3ffd2 | |
| parent | ac466a21df442c59962589ba296c702631e041b5 (diff) | |
| download | riscv-isa-sim-d920cdeeb47056e6976198384cd31f6e2e7b97da.zip riscv-isa-sim-d920cdeeb47056e6976198384cd31f6e2e7b97da.tar.gz riscv-isa-sim-d920cdeeb47056e6976198384cd31f6e2e7b97da.tar.bz2 | |
Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (#1039)
The privileged spec allows writes to pmp(i-1)cfg with locked pmp(i)cfg
(According to a recent discussion: https://github.com/riscv/riscv-isa-manual/issues/866)
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6bca99c..c5e65c8 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -248,7 +248,7 @@ bool pmpcfg_csr_t::unlogged_write(const reg_t val) noexcept { for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8; i++) { if (i < proc->n_pmp) { const bool locked = (state->pmpaddr[i]->cfg & PMP_L); - if (rlb || (!locked && !state->pmpaddr[i]->next_locked_and_tor())) { + if (rlb || !locked) { uint8_t cfg = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L); // Drop R=0 W=1 when MML = 0 // Remove the restriction when MML = 1 |