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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-12 15:41:55 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-12 15:41:55 -0800 |
| commit | b35d5757e5b9c06d143ccb55d6e9b01f47eb529c (patch) | |
| tree | d67cea7a56c54bb473ed671ea6573dc12071f132 | |
| parent | f80fc52e8842d3a5270b787a0fc57028edca5dab (diff) | |
| parent | 69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b (diff) | |
| download | riscv-isa-sim-b35d5757e5b9c06d143ccb55d6e9b01f47eb529c.zip riscv-isa-sim-b35d5757e5b9c06d143ccb55d6e9b01f47eb529c.tar.gz riscv-isa-sim-b35d5757e5b9c06d143ccb55d6e9b01f47eb529c.tar.bz2 | |
Merge pull request #1345 from scottj97/fix-1340
Fix vectored VS-level interrupts
| -rw-r--r-- | riscv/processor.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3c923ea..9739ab7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -866,7 +866,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc) reg_t vsdeleg, hsdeleg; reg_t bit = t.cause(); bool curr_virt = state.v; - bool interrupt = (bit & ((reg_t)1 << (max_xlen - 1))) != 0; + const reg_t interrupt_bit = (reg_t)1 << (max_xlen - 1); + bool interrupt = (bit & interrupt_bit) != 0; if (interrupt) { vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0; hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0; @@ -877,9 +878,10 @@ void processor_t::take_trap(trap_t& t, reg_t epc) } if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { // Handle the trap in VS-mode - reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; + const reg_t adjusted_cause = interrupt ? bit - 1 : bit; // VSSIP -> SSIP, etc + reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * adjusted_cause : 0; state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; - state.vscause->write((interrupt) ? (t.cause() - 1) : t.cause()); + state.vscause->write(adjusted_cause | (interrupt ? interrupt_bit : 0)); state.vsepc->write(epc); state.vstval->write(t.get_tval()); |