diff options
| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-04-27 13:26:40 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2024-01-11 17:43:17 -0800 |
| commit | 69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b (patch) | |
| tree | d67cea7a56c54bb473ed671ea6573dc12071f132 | |
| parent | 073510dbd46f53a71b09633a802fcd97ee38a3ac (diff) | |
| download | riscv-isa-sim-69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b.zip riscv-isa-sim-69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b.tar.gz riscv-isa-sim-69ff70fccdfbcbdb1ef01bb31a4d4cdd8d9f8b0b.tar.bz2 | |
Fix vectored VS-level interrupts
They were going to the vector for cause 10 (VSEI) even though vscause
had been correctly translated to 9 (SEI).
Fixes #1340.
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index d02c6d5..9739ab7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -879,7 +879,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { // Handle the trap in VS-mode const reg_t adjusted_cause = interrupt ? bit - 1 : bit; // VSSIP -> SSIP, etc - reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; + reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * adjusted_cause : 0; state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; state.vscause->write(adjusted_cause | (interrupt ? interrupt_bit : 0)); state.vsepc->write(epc); |