1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
|
// See LICENSE for license details.
#include "sim.h"
#include "mmu.h"
#include "htif.h"
#include "gdbserver.h"
#include <map>
#include <iostream>
#include <sstream>
#include <climits>
#include <cstdlib>
#include <cassert>
#include <signal.h>
volatile bool ctrlc_pressed = false;
static void handle_signal(int sig)
{
if (ctrlc_pressed)
exit(-1);
ctrlc_pressed = true;
signal(sig, &handle_signal);
}
sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
const std::vector<std::string>& args)
: htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
current_step(0), current_proc(0), debug(false), gdbserver(NULL)
{
signal(SIGINT, &handle_signal);
// allocate target machine's memory, shrinking it as necessary
// until the allocation succeeds
size_t memsz0 = (size_t)mem_mb << 20;
size_t quantum = 1L << 20;
if (memsz0 == 0)
memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
memsz = memsz0;
while ((mem = (char*)calloc(1, memsz)) == NULL)
memsz = (size_t)(memsz*0.9)/quantum*quantum;
if (memsz != memsz0)
fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
(unsigned long)memsz, (unsigned long)memsz0);
debug_mmu = new mmu_t(this, NULL);
for (size_t i = 0; i < procs.size(); i++) {
procs[i] = new processor_t(isa, this, i);
if (halted)
procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
}
rtc.reset(new rtc_t(procs));
make_config_string();
bus.add_device(DEBUG_START, &debug_module);
}
sim_t::~sim_t()
{
for (size_t i = 0; i < procs.size(); i++)
delete procs[i];
delete debug_mmu;
free(mem);
}
int sim_t::run()
{
if (!debug && log)
set_procs_debug(true);
while (htif->tick())
{
if (debug || ctrlc_pressed)
interactive();
else
step(INTERLEAVE);
if (gdbserver) {
gdbserver->handle();
}
}
return htif->exit_code();
}
void sim_t::step(size_t n)
{
for (size_t i = 0, steps = 0; i < n; i += steps)
{
steps = std::min(n - i, INTERLEAVE - current_step);
procs[current_proc]->step(steps);
current_step += steps;
if (current_step == INTERLEAVE)
{
current_step = 0;
procs[current_proc]->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
}
htif->tick();
}
}
}
bool sim_t::running()
{
for (size_t i = 0; i < procs.size(); i++)
if (procs[i]->running())
return true;
return false;
}
void sim_t::set_debug(bool value)
{
debug = value;
}
void sim_t::set_log(bool value)
{
log = value;
}
void sim_t::set_histogram(bool value)
{
histogram_enabled = value;
for (size_t i = 0; i < procs.size(); i++) {
procs[i]->set_histogram(histogram_enabled);
}
}
void sim_t::set_procs_debug(bool value)
{
for (size_t i=0; i< procs.size(); i++)
procs[i]->set_debug(value);
}
bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
{
if (addr + len < addr)
return false;
return bus.load(addr, len, bytes);
}
bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
{
if (addr + len < addr)
return false;
return bus.store(addr, len, bytes);
}
char* sim_t::mmio_page(reg_t addr)
{
return bus.page(addr);
}
void sim_t::make_config_string()
{
reg_t rtc_addr = EXT_IO_BASE;
bus.add_device(rtc_addr, rtc.get());
const int align = 0x1000;
reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
reg_t cpu_size = align;
uint32_t reset_vec[8] = {
0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
0x00028067, // jump straight to DRAM_BASE
0x00000000, // reserved
0, // config string pointer
0, 0, 0, 0 // trap vector
};
reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
std::stringstream s;
s << std::hex <<
"platform {\n"
" vendor ucb;\n"
" arch spike;\n"
"};\n"
"rtc {\n"
" addr 0x" << rtc_addr << ";\n"
"};\n"
"ram {\n"
" 0 {\n"
" addr 0x" << DRAM_BASE << ";\n"
" size 0x" << memsz << ";\n"
" };\n"
"};\n"
"core {\n";
for (size_t i = 0; i < procs.size(); i++) {
s <<
" " << i << " {\n"
" " << "0 {\n" << // hart 0 on core i
" isa " << procs[i]->isa_string << ";\n"
" timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
" ipi 0x" << cpu_addr << ";\n"
" };\n"
" };\n";
bus.add_device(cpu_addr, procs[i]);
cpu_addr += cpu_size;
}
s << "};\n";
config_string = s.str();
rom.insert(rom.end(), config_string.begin(), config_string.end());
rom.resize((rom.size() / align + 1) * align);
boot_rom.reset(new rom_device_t(rom));
bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
}
|
