1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
|
// See LICENSE for license details.
#include "processor.h"
#include "extension.h"
#include "common.h"
#include "config.h"
#include "sim.h"
#include "mmu.h"
#include "disasm.h"
#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#include <iostream>
#include <assert.h>
#include <limits.h>
#include <stdexcept>
#include <algorithm>
#undef STATE
#define STATE state
processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
{
parse_isa_string(isa);
register_base_instructions();
mmu = new mmu_t(sim, this);
disassembler = new disassembler_t(max_xlen);
reset();
}
processor_t::~processor_t()
{
#ifdef RISCV_ENABLE_HISTOGRAM
if (histogram_enabled)
{
fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
for (auto it : pc_histogram)
fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
}
#endif
delete mmu;
delete disassembler;
}
static void bad_isa_string(const char* isa)
{
fprintf(stderr, "error: bad --isa option %s\n", isa);
abort();
}
void processor_t::parse_isa_string(const char* str)
{
std::string lowercase, tmp;
for (const char *r = str; *r; r++)
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
const char* all_subsets = "imafdc";
max_xlen = 64;
isa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
max_xlen = 32, isa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
p += 2;
if (!*p) {
p = all_subsets;
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
} else if (*p != 'i') {
bad_isa_string(str);
}
isa_string = "rv" + std::to_string(max_xlen) + p;
isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
isa |= 1L << ('u' - 'a'); // advertise support for user mode
while (*p) {
isa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
p++;
} else if (*p == 'x') {
const char* ext = p+1, *end = ext;
while (islower(*end))
end++;
register_extension(find_extension(std::string(ext, end - ext).c_str())());
p = end;
} else {
bad_isa_string(str);
}
}
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
// advertise support for supervisor and user modes
isa |= 1L << ('s' - 'a');
isa |= 1L << ('u' - 'a');
max_isa = isa;
}
void state_t::reset()
{
memset(this, 0, sizeof(*this));
prv = PRV_M;
pc = DEFAULT_RSTVEC;
mtvec = DEFAULT_MTVEC;
load_reservation = -1;
tselect = 0;
for (unsigned int i = 0; i < num_triggers; i++)
mcontrol[i].type = 2;
}
void processor_t::set_debug(bool value)
{
debug = value;
if (ext)
ext->set_debug(value);
}
void processor_t::set_histogram(bool value)
{
histogram_enabled = value;
#ifndef RISCV_ENABLE_HISTOGRAM
if (value) {
fprintf(stderr, "PC Histogram support has not been properly enabled;");
fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
}
#endif
}
void processor_t::reset()
{
state.reset();
state.dcsr.halt = halt_on_reset;
halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
ext->reset(); // reset the extension
}
// Count number of contiguous 0 bits starting from the LSB.
static int ctz(reg_t val)
{
int res = 0;
if (val)
while ((val & 1) == 0)
val >>= 1, res++;
return res;
}
void processor_t::take_interrupt(reg_t pending_interrupts)
{
reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
if (enabled_interrupts)
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}
void processor_t::set_privilege(reg_t prv)
{
assert(prv <= PRV_M);
if (prv == PRV_H)
prv = PRV_U;
mmu->flush_tlb();
state.prv = prv;
}
void processor_t::enter_debug_mode(uint8_t cause)
{
state.dcsr.cause = cause;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
state.pc = DEBUG_ROM_START;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
{
if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
if (t.has_badaddr())
fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
t.get_badaddr());
}
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
(state.prv == PRV_H && state.dcsr.ebreakh) ||
(state.prv == PRV_S && state.dcsr.ebreaks) ||
(state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
return;
}
if (state.dcsr.cause) {
state.pc = DEBUG_ROM_EXCEPTION;
return;
}
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
if (bit & ((reg_t)1 << (max_xlen-1)))
deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
// handle the trap in S-mode
state.pc = state.stvec;
state.scause = t.cause();
state.sepc = epc;
if (t.has_badaddr())
state.sbadaddr = t.get_badaddr();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, state.prv);
s = set_field(s, MSTATUS_SIE, 0);
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
state.pc = state.mtvec;
state.mepc = epc;
state.mcause = t.cause();
if (t.has_badaddr())
state.mbadaddr = t.get_badaddr();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
s = set_field(s, MSTATUS_MPP, state.prv);
s = set_field(s, MSTATUS_MIE, 0);
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_M);
}
yield_load_reservation();
}
void processor_t::disasm(insn_t insn)
{
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
id, state.pc, bits, disassembler->disassemble(insn).c_str());
}
int processor_t::paddr_bits()
{
assert(xlen == max_xlen);
return max_xlen == 64 ? 50 : 34;
}
void processor_t::set_csr(int which, reg_t val)
{
val = zext_xlen(val);
reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
case CSR_FFLAGS:
dirty_fp_state;
state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
break;
case CSR_FRM:
dirty_fp_state;
state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
break;
case CSR_FCSR:
dirty_fp_state;
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
case CSR_MSTATUS: {
if ((val ^ state.mstatus) &
(MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
| MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
| MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
| MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
state.mstatus = (state.mstatus & ~mask) | (val & mask);
bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
if (max_xlen == 32)
state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
// spike supports the notion of xlen < max_xlen, but current priv spec
// doesn't provide a mechanism to run RV32 software on an RV64 machine
xlen = max_xlen;
break;
}
case CSR_MIP: {
reg_t mask = MIP_SSIP | MIP_STIP;
state.mip = (state.mip & ~mask) | (val & mask);
break;
}
case CSR_MIE:
state.mie = (state.mie & ~all_ints) | (val & all_ints);
break;
case CSR_MIDELEG:
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
reg_t mask = 0;
#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
#include "encoding.h"
#undef DECLARE_CAUSE
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
case CSR_MINSTRET:
case CSR_MCYCLE:
if (xlen == 32)
state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
else
state.minstret = val;
break;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
state.minstret = (val << 32) | (state.minstret << 32 >> 32);
break;
case CSR_SCOUNTEREN:
state.scounteren = val;
break;
case CSR_MCOUNTEREN:
state.mcounteren = val;
break;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
| SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
case CSR_SIP: {
reg_t mask = MIP_SSIP & state.mideleg;
return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
}
case CSR_SIE:
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
case CSR_SPTBR: {
mmu->flush_tlb();
if (max_xlen == 32)
state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
break;
}
case CSR_SEPC: state.sepc = val; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
case CSR_SBADADDR: state.sbadaddr = val; break;
case CSR_MEPC: state.mepc = val; break;
case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
case CSR_MISA: {
if (!(val & (1L << ('F' - 'A'))))
val &= ~(1L << ('D' - 'A'));
// allow MAFDC bits in MISA to be modified
reg_t mask = 0;
mask |= 1L << ('M' - 'A');
mask |= 1L << ('A' - 'A');
mask |= 1L << ('F' - 'A');
mask |= 1L << ('D' - 'A');
mask |= 1L << ('C' - 'A');
mask &= max_isa;
isa = (val & mask) | (isa & ~mask);
break;
}
case CSR_TSELECT:
if (val < state.num_triggers) {
state.tselect = val;
}
break;
case CSR_TDATA1:
{
mcontrol_t *mc = &state.mcontrol[state.tselect];
if (mc->dmode && !state.dcsr.cause) {
break;
}
mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
mc->select = get_field(val, MCONTROL_SELECT);
mc->timing = get_field(val, MCONTROL_TIMING);
mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
mc->chain = get_field(val, MCONTROL_CHAIN);
mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
mc->m = get_field(val, MCONTROL_M);
mc->h = get_field(val, MCONTROL_H);
mc->s = get_field(val, MCONTROL_S);
mc->u = get_field(val, MCONTROL_U);
mc->execute = get_field(val, MCONTROL_EXECUTE);
mc->store = get_field(val, MCONTROL_STORE);
mc->load = get_field(val, MCONTROL_LOAD);
// Assume we're here because of csrw.
if (mc->execute)
mc->timing = 0;
trigger_updated();
}
break;
case CSR_TDATA2:
if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
break;
}
if (state.tselect < state.num_triggers) {
state.tdata2[state.tselect] = val;
}
break;
case CSR_DCSR:
state.dcsr.prv = get_field(val, DCSR_PRV);
state.dcsr.step = get_field(val, DCSR_STEP);
// TODO: ndreset and fullreset
state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
state.dcsr.halt = get_field(val, DCSR_HALT);
break;
case CSR_DPC:
state.dpc = val;
break;
case CSR_DSCRATCH:
state.dscratch = val;
break;
}
}
reg_t processor_t::get_csr(int which)
{
uint32_t ctr_en = -1;
if (state.prv < PRV_M)
ctr_en &= state.mcounteren;
if (state.prv < PRV_S)
ctr_en &= state.scounteren;
bool ctr_ok = (ctr_en >> (which & 31)) & 1;
if (ctr_ok) {
if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
return 0;
if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
return 0;
}
if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
return 0;
if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
return 0;
if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
return 0;
switch (which)
{
case CSR_FFLAGS:
require_fp;
if (!supports_extension('F'))
break;
return state.fflags;
case CSR_FRM:
require_fp;
if (!supports_extension('F'))
break;
return state.frm;
case CSR_FCSR:
require_fp;
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
case CSR_INSTRET:
case CSR_CYCLE:
if (ctr_ok)
return state.minstret;
break;
case CSR_MINSTRET:
case CSR_MCYCLE:
return state.minstret;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
if (xlen == 32)
return state.minstret >> 32;
break;
case CSR_SCOUNTEREN: return state.scounteren;
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
| SSTATUS_XS | SSTATUS_SUM;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
return sstatus;
}
case CSR_SIP: return state.mip & state.mideleg;
case CSR_SIE: return state.mie & state.mideleg;
case CSR_SEPC: return state.sepc;
case CSR_SBADADDR: return state.sbadaddr;
case CSR_STVEC: return state.stvec;
case CSR_SCAUSE:
if (max_xlen > xlen)
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
return state.scause;
case CSR_SPTBR:
if (get_field(state.mstatus, MSTATUS_TVM))
require_privilege(PRV_M);
return state.sptbr;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
case CSR_MIE: return state.mie;
case CSR_MEPC: return state.mepc;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MBADADDR: return state.mbadaddr;
case CSR_MISA: return isa;
case CSR_MARCHID: return 0;
case CSR_MIMPID: return 0;
case CSR_MVENDORID: return 0;
case CSR_MHARTID: return id;
case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
case CSR_TSELECT: return state.tselect;
case CSR_TDATA1:
if (state.tselect < state.num_triggers) {
reg_t v = 0;
mcontrol_t *mc = &state.mcontrol[state.tselect];
v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
v = set_field(v, MCONTROL_SELECT, mc->select);
v = set_field(v, MCONTROL_TIMING, mc->timing);
v = set_field(v, MCONTROL_ACTION, mc->action);
v = set_field(v, MCONTROL_CHAIN, mc->chain);
v = set_field(v, MCONTROL_MATCH, mc->match);
v = set_field(v, MCONTROL_M, mc->m);
v = set_field(v, MCONTROL_H, mc->h);
v = set_field(v, MCONTROL_S, mc->s);
v = set_field(v, MCONTROL_U, mc->u);
v = set_field(v, MCONTROL_EXECUTE, mc->execute);
v = set_field(v, MCONTROL_STORE, mc->store);
v = set_field(v, MCONTROL_LOAD, mc->load);
return v;
} else {
return 0;
}
break;
case CSR_TDATA2:
if (state.tselect < state.num_triggers) {
return state.tdata2[state.tselect];
} else {
return 0;
}
break;
case CSR_TDATA3: return 0;
case CSR_DCSR:
{
uint32_t v = 0;
v = set_field(v, DCSR_XDEBUGVER, 1);
v = set_field(v, DCSR_NDRESET, 0);
v = set_field(v, DCSR_FULLRESET, 0);
v = set_field(v, DCSR_PRV, state.dcsr.prv);
v = set_field(v, DCSR_STEP, state.dcsr.step);
v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
v = set_field(v, DCSR_STOPCYCLE, 0);
v = set_field(v, DCSR_STOPTIME, 0);
v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
v = set_field(v, DCSR_HALT, state.dcsr.halt);
v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
return v;
}
case CSR_DPC:
return state.dpc;
case CSR_DSCRATCH:
return state.dscratch;
}
throw trap_illegal_instruction();
}
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
{
throw trap_illegal_instruction();
}
insn_func_t processor_t::decode_insn(insn_t insn)
{
// look up opcode in hash table
size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
insn_desc_t desc = opcode_cache[idx];
if (unlikely(insn.bits() != desc.match)) {
// fall back to linear search
insn_desc_t* p = &instructions[0];
while ((insn.bits() & p->mask) != p->match)
p++;
desc = *p;
if (p->mask != 0 && p > &instructions[0]) {
if (p->match != (p-1)->match && p->match != (p+1)->match) {
// move to front of opcode list to reduce miss penalty
while (--p >= &instructions[0])
*(p+1) = *p;
instructions[0] = desc;
}
}
opcode_cache[idx] = desc;
opcode_cache[idx].match = insn.bits();
}
return xlen == 64 ? desc.rv64 : desc.rv32;
}
void processor_t::register_insn(insn_desc_t desc)
{
instructions.push_back(desc);
}
void processor_t::build_opcode_map()
{
struct cmp {
bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
if (lhs.match == rhs.match)
return lhs.mask > rhs.mask;
return lhs.match > rhs.match;
}
};
std::sort(instructions.begin(), instructions.end(), cmp());
for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
}
void processor_t::register_extension(extension_t* x)
{
for (auto insn : x->get_instructions())
register_insn(insn);
build_opcode_map();
for (auto disasm_insn : x->get_disasms())
disassembler->add_insn(disasm_insn);
if (ext != NULL)
throw std::logic_error("only one extension may be registered");
ext = x;
x->set_processor(this);
}
void processor_t::register_base_instructions()
{
#define DECLARE_INSN(name, match, mask) \
insn_bits_t name##_match = (match), name##_mask = (mask);
#include "encoding.h"
#undef DECLARE_INSN
#define DEFINE_INSN(name) \
REGISTER_INSN(this, name, name##_match, name##_mask)
#include "insn_list.h"
#undef DEFINE_INSN
register_insn({0, 0, &illegal_instruction, &illegal_instruction});
build_opcode_map();
}
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
switch (addr)
{
case 0:
if (len <= 4) {
memset(bytes, 0, len);
bytes[0] = get_field(state.mip, MIP_MSIP);
return true;
}
break;
}
return false;
}
bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
{
switch (addr)
{
case 0:
if (len <= 4) {
state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
return true;
}
break;
}
return false;
}
void processor_t::trigger_updated()
{
mmu->flush_tlb();
mmu->check_triggers_fetch = false;
mmu->check_triggers_load = false;
mmu->check_triggers_store = false;
for (unsigned i = 0; i < state.num_triggers; i++) {
if (state.mcontrol[i].execute) {
mmu->check_triggers_fetch = true;
}
if (state.mcontrol[i].load) {
mmu->check_triggers_load = true;
}
if (state.mcontrol[i].store) {
mmu->check_triggers_store = true;
}
}
}
|