// See LICENSE for license details. #ifndef _RISCV_SIM_H #define _RISCV_SIM_H #include "config.h" #ifdef HAVE_BOOST_ASIO #include #include #include #endif #include "cfg.h" #include "debug_module.h" #include "devices.h" #include "log_file.h" #include "processor.h" #include "simif.h" #include #include #include #include #include #include class mmu_t; class remote_bitbang_t; // this class encapsulates the processors and memory in a RISC-V machine. class sim_t : public htif_t, public simif_t { public: sim_t(const cfg_t *cfg, bool halted, std::vector> mems, std::vector> plugin_devices, const std::vector& args, const debug_module_config_t &dm_config, const char *log_path, bool dtb_enabled, const char *dtb_file, #ifdef HAVE_BOOST_ASIO boost::asio::io_service *io_service_ptr_ctor, boost::asio::ip::tcp::acceptor *acceptor_ptr_ctor, // option -s #endif FILE *cmd_file); // needed for command line option --cmd ~sim_t(); // run the simulation to completion int run(); void set_debug(bool value); void set_histogram(bool value); // Configure logging // // If enable_log is true, an instruction trace will be generated. If // enable_commitlog is true, so will the commit results (if this // build was configured without support for commit logging, the // function will print an error message and abort). void configure_log(bool enable_log, bool enable_commitlog); void set_procs_debug(bool value); void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } // Callback for processors to let the simulation know they were reset. void proc_reset(unsigned id); private: isa_parser_t isa; const cfg_t * const cfg; std::vector> mems; std::vector> plugin_devices; mmu_t* debug_mmu; // debug port into main memory std::vector procs; std::pair initrd_range; std::string dts; std::string dtb; std::string dtb_file; bool dtb_enabled; std::unique_ptr boot_rom; std::unique_ptr clint; std::unique_ptr plic; std::unique_ptr ns16550; bus_t bus; log_file_t log_file; FILE *cmd_file; // pointer to debug command input file #ifdef HAVE_BOOST_ASIO // the following are needed for command socket interface boost::asio::io_service *io_service_ptr; boost::asio::ip::tcp::acceptor *acceptor_ptr; std::unique_ptr socket_ptr; std::string rin(boost::asio::streambuf *bout_ptr); // read input command string void wout(boost::asio::streambuf *bout_ptr); // write output to socket #endif std::ostream sout_; // used for socket and terminal interface processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; bool histogram_enabled; // provide a histogram of PCs bool log; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines char* addr_to_mem(reg_t addr); bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); void make_dtb(); void set_rom(); const char* get_symbol(uint64_t addr); // presents a prompt for introspection into the simulation void interactive(); // functions that help implement interactive() void interactive_help(const std::string& cmd, const std::vector& args); void interactive_quit(const std::string& cmd, const std::vector& args); void interactive_run(const std::string& cmd, const std::vector& args, bool noisy); void interactive_run_noisy(const std::string& cmd, const std::vector& args); void interactive_run_silent(const std::string& cmd, const std::vector& args); void interactive_vreg(const std::string& cmd, const std::vector& args); void interactive_reg(const std::string& cmd, const std::vector& args); void interactive_freg(const std::string& cmd, const std::vector& args); void interactive_fregh(const std::string& cmd, const std::vector& args); void interactive_fregs(const std::string& cmd, const std::vector& args); void interactive_fregd(const std::string& cmd, const std::vector& args); void interactive_pc(const std::string& cmd, const std::vector& args); void interactive_mem(const std::string& cmd, const std::vector& args); void interactive_str(const std::string& cmd, const std::vector& args); void interactive_until(const std::string& cmd, const std::vector& args, bool noisy); void interactive_until_silent(const std::string& cmd, const std::vector& args); void interactive_until_noisy(const std::string& cmd, const std::vector& args); reg_t get_reg(const std::vector& args); freg_t get_freg(const std::vector& args); reg_t get_mem(const std::vector& args); reg_t get_pc(const std::vector& args); friend class processor_t; friend class mmu_t; friend class debug_module_t; // htif friend void sim_thread_main(void*); void main(); context_t* host; context_t target; void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); size_t chunk_align() { return 8; } size_t chunk_max_size() { return 8; } void set_target_endianness(memif_endianness_t endianness); memif_endianness_t get_target_endianness() const; public: // Initialize this after procs, because in debug_module_t::reset() we // enumerate processors, which segfaults if procs hasn't been initialized // yet. debug_module_t debug_module; }; extern volatile bool ctrlc_pressed; #endif