From d85446f81f3c9405a2041ab5235281a3bbaab77f Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Thu, 8 Sep 2022 21:16:35 +0800
Subject: Remove unnecessary argument alu(always false) from macro
 require_vector_novtype

---
 riscv/decode.h         | 4 +---
 riscv/insns/vsetivli.h | 2 +-
 riscv/insns/vsetvl.h   | 2 +-
 riscv/insns/vsetvli.h  | 2 +-
 riscv/v_ext_macros.h   | 4 ++--
 5 files changed, 6 insertions(+), 8 deletions(-)

(limited to 'riscv')

diff --git a/riscv/decode.h b/riscv/decode.h
index 874d239..5fb0358 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -306,12 +306,10 @@ do { \
     WRITE_VSTATUS; \
     dirty_vs_state; \
   } while (0);
-#define require_vector_novtype(is_log, alu) \
+#define require_vector_novtype(is_log) \
   do { \
     require_vector_vs; \
     require_extension('V'); \
-    if (alu && !P.VU.vstart_alu) \
-      require(P.VU.vstart->read() == 0); \
     if (is_log) \
       WRITE_VSTATUS; \
     dirty_vs_state; \
diff --git a/riscv/insns/vsetivli.h b/riscv/insns/vsetivli.h
index 04900a2..f880e96 100644
--- a/riscv/insns/vsetivli.h
+++ b/riscv/insns/vsetivli.h
@@ -1,2 +1,2 @@
-require_vector_novtype(false, false);
+require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10()));
diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h
index 2969edc..4d03542 100644
--- a/riscv/insns/vsetvl.h
+++ b/riscv/insns/vsetvl.h
@@ -1,2 +1,2 @@
-require_vector_novtype(false, false);
+require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2));
diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h
index 7b1f1d7..d1f43b5 100644
--- a/riscv/insns/vsetvli.h
+++ b/riscv/insns/vsetvli.h
@@ -1,2 +1,2 @@
-require_vector_novtype(false, false);
+require_vector_novtype(false);
 WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11()));
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h
index 71a5401..2893306 100644
--- a/riscv/v_ext_macros.h
+++ b/riscv/v_ext_macros.h
@@ -1317,7 +1317,7 @@ reg_t index[P.VU.vlmax]; \
   p->VU.vstart->write(0);
 
 #define VI_LD_WHOLE(elt_width) \
-  require_vector_novtype(true, false); \
+  require_vector_novtype(true); \
   require(sizeof(elt_width ## _t) * 8 <= P.VU.ELEN); \
   const reg_t baseAddr = RS1; \
   const reg_t vd = insn.rd(); \
@@ -1349,7 +1349,7 @@ reg_t index[P.VU.vlmax]; \
   P.VU.vstart->write(0);
 
 #define VI_ST_WHOLE \
-  require_vector_novtype(true, false); \
+  require_vector_novtype(true); \
   const reg_t baseAddr = RS1; \
   const reg_t vs3 = insn.rd(); \
   const reg_t len = insn.v_nf() + 1; \
-- 
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