From d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 5 Nov 2013 21:01:34 -0800 Subject: correctly trap when SR_EA is disabled --- riscv/decode.h | 1 + riscv/rocc.cc | 1 + riscv/trap.h | 1 + 3 files changed, 3 insertions(+) (limited to 'riscv') diff --git a/riscv/decode.h b/riscv/decode.h index 7cf7eac..3fc2be7 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -145,6 +145,7 @@ private: #else # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled() #endif +#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled() #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \ diff --git a/riscv/rocc.cc b/riscv/rocc.cc index 7988c01..e51aee5 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -5,6 +5,7 @@ #define customX(n) \ static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ { \ + require_accelerator; \ rocc_t* rocc = static_cast(p->get_extension()); \ rocc_insn_union_t u; \ u.i = insn; \ diff --git a/riscv/trap.h b/riscv/trap.h index 9a1a2f9..bd7e0ee 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -54,5 +54,6 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) +DECLARE_TRAP(12, accelerator_disabled) #endif -- cgit v1.1