From 2c9648735e5f7ba6d3e68bd20f6b9b599743016c Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 22 Sep 2021 17:27:47 -0700
Subject: Convert dscratch0/1 to csr_t

---
 riscv/csrs.cc      | 11 +++++++++++
 riscv/csrs.h       |  7 +++++++
 riscv/processor.cc | 20 ++------------------
 riscv/processor.h  |  1 -
 4 files changed, 20 insertions(+), 19 deletions(-)

(limited to 'riscv')

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index 479dd27..0badeaa 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -1036,3 +1036,14 @@ bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept {
   vals[state->tselect->read()] = val;
   return true;
 }
+
+
+debug_mode_csr_t::debug_mode_csr_t(processor_t* const proc, const reg_t addr):
+  basic_csr_t(proc, addr, 0) {
+}
+
+void debug_mode_csr_t::verify_permissions(insn_t insn, bool write) const {
+  basic_csr_t::verify_permissions(insn, write);
+  if (!state->debug_mode)
+    throw trap_illegal_instruction(insn.bits());
+}
diff --git a/riscv/csrs.h b/riscv/csrs.h
index 058fb42..c293554 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -527,6 +527,13 @@ class tdata2_csr_t: public csr_t {
   std::vector<reg_t> vals;
 };
 
+// For CSRs that are only writable from debug mode
+class debug_mode_csr_t: public basic_csr_t {
+ public:
+  debug_mode_csr_t(processor_t* const proc, const reg_t addr);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+};
+
 typedef std::shared_ptr<tdata2_csr_t> tdata2_csr_t_p;
 
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index e32acda..2fa9118 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -497,8 +497,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_SSTATUS] = sstatus = std::make_shared<sstatus_csr_t>(proc, nonvirtual_sstatus, vsstatus);
 
   dpc = 0;
-  dscratch0 = 0;
-  dscratch1 = 0;
+  csrmap[CSR_DSCRATCH0] = std::make_shared<debug_mode_csr_t>(proc, CSR_DSCRATCH0);
+  csrmap[CSR_DSCRATCH1] = std::make_shared<debug_mode_csr_t>(proc, CSR_DSCRATCH1);
   memset(&this->dcsr, 0, sizeof(this->dcsr));
 
   csrmap[CSR_TSELECT] = tselect = std::make_shared<tselect_csr_t>(proc, CSR_TSELECT);
@@ -1007,12 +1007,6 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_DPC:
       state.dpc = val & ~(reg_t)1;
       break;
-    case CSR_DSCRATCH0:
-      state.dscratch0 = val;
-      break;
-    case CSR_DSCRATCH1:
-      state.dscratch1 = val;
-      break;
     case CSR_VSTART:
       dirty_vs_state;
       VU.vstart = val & (VU.get_vlen() - 1);
@@ -1058,8 +1052,6 @@ void processor_t::set_csr(int which, reg_t val)
 
     case CSR_DCSR:
     case CSR_DPC:
-    case CSR_DSCRATCH0:
-    case CSR_DSCRATCH1:
     case CSR_SENTROPY:
       LOG_CSR(which);
       break;
@@ -1144,14 +1136,6 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
       if (!state.debug_mode)
         break;
       ret(state.dpc & pc_alignment_mask());
-    case CSR_DSCRATCH0:
-      if (!state.debug_mode)
-        break;
-      ret(state.dscratch0);
-    case CSR_DSCRATCH1:
-      if (!state.debug_mode)
-        break;
-      ret(state.dscratch1);
     case CSR_VSTART:
       require_vector_vs;
       if (!extension_enabled('V'))
diff --git a/riscv/processor.h b/riscv/processor.h
index b2aadf5..bd1c85b 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -202,7 +202,6 @@ struct state_t
   csr_t_p vsatp;
 
   reg_t dpc;
-  reg_t dscratch0, dscratch1;
   dcsr_t dcsr;
   csr_t_p tselect;
   mcontrol_t mcontrol[num_triggers];
-- 
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