From 970959e4b096b07b5af94030b515180503123524 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Thu, 16 May 2019 19:21:47 -0700
Subject: rvv: fix missng empty line

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/riscv.mk.in | 1 +
 1 file changed, 1 insertion(+)

(limited to 'riscv/riscv.mk.in')

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 5891aeb..98f7cdc 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -485,6 +485,7 @@ riscv_insn_ext_v_alu_int = \
 	vxor_vi \
 	vxor_vv \
 	vxor_vx \
+
 riscv_insn_ext_v_alu_fp = \
 	vfadd_vf \
 	vfadd_vv \
-- 
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