From 84a98f6f718cd482710238042eac3d2b855c6768 Mon Sep 17 00:00:00 2001 From: "soberl@nvidia.com" Date: Tue, 3 May 2022 19:38:07 -0700 Subject: Implement the new csr mseccfg for ePMP as dummy --- riscv/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 8797ab1..96fdc54 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -179,6 +179,8 @@ struct state_t tdata2_csr_t_p tdata2; bool debug_mode; + mseccfg_csr_t_p mseccfg; + static const int max_pmp = 16; pmpaddr_csr_t_p pmpaddr[max_pmp]; -- cgit v1.1 From 68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 May 2022 14:06:27 -0700 Subject: Remove insn_func_t::supported field The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759. Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665. --- riscv/processor.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 96fdc54..ec1b400 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -29,7 +29,6 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); struct insn_desc_t { - bool supported; insn_bits_t match; insn_bits_t mask; insn_func_t rv32i; @@ -39,9 +38,6 @@ struct insn_desc_t insn_func_t func(int xlen, bool rve) { - if (!supported) - return NULL; - if (rve) return xlen == 64 ? rv64e : rv32e; else @@ -50,7 +46,7 @@ struct insn_desc_t static insn_desc_t illegal() { - return {true, 0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; + return {0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; } }; -- cgit v1.1 From 2aedbdd01911a42565cd6d154f82fa00a66410cd Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Fri, 1 Jul 2022 16:09:02 +0800 Subject: remove multi blank lines --- riscv/processor.h | 1 - 1 file changed, 1 deletion(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index ec1b400..0c6a6b2 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -118,7 +118,6 @@ struct type_sew_t<64> using type=int64_t; }; - // architectural state of a RISC-V hart struct state_t { -- cgit v1.1 From 2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 6 Jul 2022 10:45:04 +0800 Subject: add support for csrs of smstateen extensions --- riscv/processor.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 0c6a6b2..727c404 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -186,6 +186,10 @@ struct state_t csr_t_p senvcfg; csr_t_p henvcfg; + csr_t_p mstateen[4]; + csr_t_p sstateen[4]; + csr_t_p hstateen[4]; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This -- cgit v1.1 From 3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Wed, 13 Jul 2022 10:45:41 -0700 Subject: Properly log mstatush side effect updates These have never been logged properly. --- riscv/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 727c404..347ae16 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -133,6 +133,7 @@ struct state_t bool v; misa_csr_t_p misa; mstatus_csr_t_p mstatus; + csr_t_p mstatush; csr_t_p mepc; csr_t_p mtval; csr_t_p mtvec; -- cgit v1.1 From 3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Fri, 8 Jul 2022 20:30:02 +0800 Subject: add support for time/timeh/htimedelta/htimedeltah csrs --- riscv/processor.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 347ae16..b415402 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -191,6 +191,9 @@ struct state_t csr_t_p sstateen[4]; csr_t_p hstateen[4]; + csr_t_p htimedelta; + time_counter_csr_t_p time; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This -- cgit v1.1 From 5672c4a41ad7a9af011d385962c175a5a6012fd9 Mon Sep 17 00:00:00 2001 From: i2h2 <110197402+i2h2@users.noreply.github.com> Date: Wed, 3 Aug 2022 16:01:57 -0600 Subject: Add Sstc support. (#1057) --- riscv/processor.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index b415402..88ddf70 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -193,6 +193,10 @@ struct state_t csr_t_p htimedelta; time_counter_csr_t_p time; + csr_t_p time_proxy; + + csr_t_p stimecmp; + csr_t_p vstimecmp; bool serialized; // whether timer CSRs are in a well-defined state -- cgit v1.1 From ba10686fd18f3fbb036ca04b906deb57e7d1fe54 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Mon, 4 Jul 2022 21:31:09 +0800 Subject: add support for sscofpmf extension v0.5.2 since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently --- riscv/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..9b821b3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -145,6 +145,7 @@ struct state_t csr_t_p medeleg; csr_t_p mideleg; csr_t_p mcounteren; + csr_t_p mevent[29]; csr_t_p scounteren; csr_t_p sepc; csr_t_p stval; -- cgit v1.1 From ce34edb0eecec520d6d2cfec5bda57ca90a69f14 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 10 Aug 2022 22:55:07 +0800 Subject: Add space between if/while/switch and '(' Add space between ')' and '{' --- riscv/processor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..073b25b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -406,7 +406,7 @@ public: // vector element for varies SEW template - T& elt(reg_t vReg, reg_t n, bool is_write = false){ + T& elt(reg_t vReg, reg_t n, bool is_write = false) { assert(vsew != 0); assert((VLEN >> 3)/sizeof(T) > 0); reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); @@ -453,7 +453,7 @@ public: vstart_alu(false) { } - ~vectorUnit_t(){ + ~vectorUnit_t() { free(reg_file); reg_file = 0; } -- cgit v1.1 From 711215124bdf5bed4d1941c0a023a1d6881aca1d Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Tue, 6 Sep 2022 12:56:23 -0700 Subject: Remove obsolete enum trigger_operation_t Moved to triggers.h and renamed in a2a2587426e57f6207d5389620e9109bc0f82e6b, but the old enum was mistakenly left behind. --- riscv/processor.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 073b25b..3937211 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -218,12 +218,6 @@ struct state_t #endif }; -typedef enum { - OPERATION_EXECUTE, - OPERATION_STORE, - OPERATION_LOAD, -} trigger_operation_t; - // Count number of contiguous 1 bits starting from the LSB. static int cto(reg_t val) { -- cgit v1.1 From ac89fe6ce3150dc651238991235b7f2e8ac93aec Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 15:31:42 -0700 Subject: Fix unused-function warning on sometimes-used function cto --- riscv/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 7fc4be7..441e522 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -220,7 +220,7 @@ struct state_t }; // Count number of contiguous 1 bits starting from the LSB. -static int cto(reg_t val) +static inline int cto(reg_t val) { int res = 0; while ((val & 1) == 1) -- cgit v1.1 From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 17:34:33 -0700 Subject: Suppress most unused variable warnings --- riscv/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 441e522..fc80914 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -401,7 +401,7 @@ public: // vector element for varies SEW template - T& elt(reg_t vReg, reg_t n, bool is_write = false) { + T& elt(reg_t vReg, reg_t n, bool UNUSED is_write = false) { assert(vsew != 0); assert((VLEN >> 3)/sizeof(T) > 0); reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); -- cgit v1.1