From eb2cce0c99075f89e77b0c1db92108f9c49ccab0 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 3 Aug 2022 10:32:51 +0800
Subject: add stateen related check to frm/fflags and then apply to fcsr
 implicitly

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6d0d349..ddb0344 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -393,7 +393,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_FFLAGS] = fflags = std::make_shared<float_csr_t>(proc, CSR_FFLAGS, FSR_AEXC >> FSR_AEXC_SHIFT, 0);
   csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0);
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
-  csrmap[CSR_FCSR] = std::make_shared<fcsr_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
+  csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
 
   csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED);
 
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