From 84a98f6f718cd482710238042eac3d2b855c6768 Mon Sep 17 00:00:00 2001
From: "soberl@nvidia.com" <soberl@nvidia.com>
Date: Tue, 3 May 2022 19:38:07 -0700
Subject: Implement the new csr mseccfg for ePMP as dummy

---
 riscv/processor.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ad9944e..9ce9287 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -358,6 +358,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   debug_mode = false;
   single_step = STEP_NONE;
 
+  csrmap[CSR_MSECCFG] = mseccfg = std::make_shared<mseccfg_csr_t>(proc, CSR_MSECCFG);
+
   for (int i = 0; i < max_pmp; ++i) {
     csrmap[CSR_PMPADDR0 + i] = pmpaddr[i] = std::make_shared<pmpaddr_csr_t>(proc, CSR_PMPADDR0 + i);
   }
-- 
cgit v1.1


From fc35f34fd0f5307354cc25ae8018cda62f834e25 Mon Sep 17 00:00:00 2001
From: Ryan Buchner <ryan.buchner@arilinc.com>
Date: Tue, 10 May 2022 15:22:11 -0700
Subject: Change henvcfg csr to a henvcfg_csr_t

To do so implemented henvcfg_csr_t.

henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9ce9287..72f2d47 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -387,7 +387,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<masked_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
   const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0);
-  csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<masked_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0);
+  csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0, menvcfg);
 
   serialized = false;
 
-- 
cgit v1.1


From ea70a9359daf5780b815b68aa9cdc7b2a71d2f8c Mon Sep 17 00:00:00 2001
From: Ryan Buchner <ryan.buchner@arilinc.com>
Date: Sat, 7 May 2022 22:25:00 -0700
Subject: Add PBMTE bit to menvcfg and henvcfg mask values

Also make PBMTE set on reset for backward compatibility.

Since before Spike proceeded as if these bits were set if the extension was enabled.
---
 riscv/processor.cc | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 72f2d47..661058c 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -380,14 +380,18 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MVENDORID] = std::make_shared<const_csr_t>(proc, CSR_MVENDORID, 0);
   csrmap[CSR_MHARTID] = std::make_shared<const_csr_t>(proc, CSR_MHARTID, proc->get_id());
   const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
-                             (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0);
-  csrmap[CSR_MENVCFG] = menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, 0);
+                             (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
+                             (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
+  const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
+  csrmap[CSR_MENVCFG] = menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
   const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
   csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<masked_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
   const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
-                             (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0);
-  csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, 0, menvcfg);
+                             (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
+                             (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
+  const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
+  csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
 
   serialized = false;
 
-- 
cgit v1.1


From 11f5942b7d8211e61b5ad9259d118033692c0759 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 12 May 2022 14:05:37 -0700
Subject: Don't register instructions that aren't supported

These add to the length of the instruction list without providing
an apparent benefit.
---
 riscv/processor.cc | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9ce9287..dd61cae 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -959,14 +959,16 @@ void processor_t::register_base_instructions()
     extern reg_t rv64i_##name(processor_t*, insn_t, reg_t); \
     extern reg_t rv32e_##name(processor_t*, insn_t, reg_t); \
     extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \
-    register_insn((insn_desc_t) { \
-      name##_supported, \
-      name##_match, \
-      name##_mask, \
-      rv32i_##name, \
-      rv64i_##name, \
-      rv32e_##name, \
-      rv64e_##name});
+    if (name##_supported) { \
+      register_insn((insn_desc_t) { \
+        name##_supported, \
+        name##_match, \
+        name##_mask, \
+        rv32i_##name, \
+        rv64i_##name, \
+        rv32e_##name, \
+        rv64e_##name}); \
+    }
   #include "insn_list.h"
   #undef DEFINE_INSN
 
-- 
cgit v1.1


From 68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 12 May 2022 14:06:27 -0700
Subject: Remove insn_func_t::supported field

The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759.

Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665.
---
 riscv/processor.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index dd61cae..2cc1003 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -961,7 +961,6 @@ void processor_t::register_base_instructions()
     extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \
     if (name##_supported) { \
       register_insn((insn_desc_t) { \
-        name##_supported, \
         name##_match, \
         name##_mask, \
         rv32i_##name, \
-- 
cgit v1.1


From 0676421e93180f4e2421fb5058f5e6c1de8ae2c1 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 12 May 2022 14:18:02 -0700
Subject: Assert that nullptrs can't make their way into the instructions list

---
 riscv/processor.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2cc1003..98ae637 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -907,6 +907,8 @@ insn_func_t processor_t::decode_insn(insn_t insn)
 
 void processor_t::register_insn(insn_desc_t desc)
 {
+  assert(desc.rv32i && desc.rv64i && desc.rv32e && desc.rv64e);
+
   instructions.push_back(desc);
 }
 
-- 
cgit v1.1


From e66e2e2b09c04acf733089658cf32a27708b8d16 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 12 May 2022 14:18:47 -0700
Subject: Remove now-unnecessary null check from decode_insn

Fixes bug introduced in 5b7cdbe1cf75112bd2a472b7490b15fa7078d798
---
 riscv/processor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 98ae637..787a795 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -881,11 +881,11 @@ insn_func_t processor_t::decode_insn(insn_t insn)
 
   bool rve = extension_enabled('E');
 
-  if (unlikely(insn.bits() != desc.match || !desc.func(xlen, rve))) {
+  if (unlikely(insn.bits() != desc.match)) {
     // fall back to linear search
     int cnt = 0;
     insn_desc_t* p = &instructions[0];
-    while ((insn.bits() & p->mask) != p->match || !desc.func(xlen, rve))
+    while ((insn.bits() & p->mask) != p->match)
       p++, cnt++;
     desc = *p;
 
-- 
cgit v1.1


From a0298a33e7b2091ba8d9f3a20838d96dc1164cac Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Thu, 19 May 2022 17:11:07 -0700
Subject: Move ebreak* logic from take_trap into instructions. (#1006)

Now that logic only affects ebreak instructions, and does not affect
triggers that also cause a trap to be taken.

Fixes #725. Although like Paul, I don't have a test for this case.

Introduce trap_debug_mode so so ebreak instructions can force entry into
debug mode.
---
 riscv/processor.cc | 8 --------
 1 file changed, 8 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index a9003a8..bb41248 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -720,14 +720,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     return;
   }
 
-  if (t.cause() == CAUSE_BREAKPOINT && (
-              (state.prv == PRV_M && state.dcsr->ebreakm) ||
-              (state.prv == PRV_S && state.dcsr->ebreaks) ||
-              (state.prv == PRV_U && state.dcsr->ebreaku))) {
-    enter_debug_mode(DCSR_CAUSE_SWBP);
-    return;
-  }
-
   // By default, trap to M-mode, unless delegated to HS-mode or VS-mode
   reg_t vsdeleg, hsdeleg;
   reg_t bit = t.cause();
-- 
cgit v1.1


From 7d943d740afb6a42b50c979800608c6fb1614d0c Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 6 Jun 2022 20:36:05 -0700
Subject: Don't mask instruction bits

No longer needed, since they are no longer sign-extended.

Fixes #1022 by eliminating undefined behavior (64-bit instructions
resulted in a shift amount equal to the datatype width).
---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index bb41248..c4ca0bc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -796,7 +796,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
 
 void processor_t::disasm(insn_t insn)
 {
-  uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+  uint64_t bits = insn.bits();
   if (last_pc != state.pc || last_bits != bits) {
     std::stringstream s;  // first put everything in a string, later send it to output
 
-- 
cgit v1.1


From 9b66f89b8102f032f721fe332819325508aa3b95 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:43:57 +0800
Subject: modify mstatush_csr_t to general rv32_high_csr_t

---
 riscv/processor.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c4ca0bc..7ffc8d1 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -190,7 +190,11 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   v = false;
   csrmap[CSR_MISA] = misa = std::make_shared<misa_csr_t>(proc, CSR_MISA, max_isa);
   csrmap[CSR_MSTATUS] = mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
-  if (xlen == 32) csrmap[CSR_MSTATUSH] = std::make_shared<mstatush_csr_t>(proc, CSR_MSTATUSH, mstatus);
+
+  if (xlen == 32) {
+    const reg_t mstatush_mask = MSTATUSH_MPV | MSTATUSH_GVA | MSTATUSH_SBE | MSTATUSH_MBE;
+    csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatush_mask, mstatus);
+  }
   csrmap[CSR_MEPC] = mepc = std::make_shared<epc_csr_t>(proc, CSR_MEPC);
   csrmap[CSR_MTVAL] = mtval = std::make_shared<basic_csr_t>(proc, CSR_MTVAL, 0);
   csrmap[CSR_MSCRATCH] = std::make_shared<basic_csr_t>(proc, CSR_MSCRATCH, 0);
-- 
cgit v1.1


From 2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:45:04 +0800
Subject: add support for csrs of smstateen extensions

---
 riscv/processor.cc | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7ffc8d1..1c33911 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -397,6 +397,28 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
   csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
 
+  if (proc->extension_enabled_const(EXT_SMSTATEEN)) {
+    const reg_t sstateen0_mask = (proc->extension_enabled(EXT_ZFINX) ? SSTATEEN0_FCSR : 0) | SSTATEEN0_CS;
+    const reg_t hstateen0_mask = sstateen0_mask | HSTATEEN0_SENVCFG | HSTATEEN_SSTATEEN;
+    const reg_t mstateen0_mask = hstateen0_mask;
+    for (int i = 0; i < 4; i++) {
+      const reg_t mstateen_mask = i == 0 ? mstateen0_mask : MSTATEEN_HSTATEEN;
+      csrmap[CSR_MSTATEEN0 + i] = mstateen[i] = std::make_shared<masked_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen_mask, 0);
+      if (xlen == 32) {
+        csrmap[CSR_MSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATEEN0H + i, -1, mstateen[i]);
+      }
+
+      const reg_t hstateen_mask = i == 0 ? hstateen0_mask : HSTATEEN_SSTATEEN;
+      csrmap[CSR_HSTATEEN0 + i] = hstateen[i] = std::make_shared<hstateen_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen_mask, 0, i);
+      if (xlen == 32) {
+        csrmap[CSR_HSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_HSTATEEN0H + i, -1, hstateen[i]);
+      }
+
+      const reg_t sstateen_mask = i == 0 ? sstateen0_mask : 0;
+      csrmap[CSR_SSTATEEN0 + i] = sstateen[i] = std::make_shared<sstateen_csr_t>(proc, CSR_HSTATEEN0 + i, sstateen_mask, 0, i);
+    }
+  }
+
   serialized = false;
 
 #ifdef RISCV_ENABLE_COMMITLOG
-- 
cgit v1.1


From 11dacaedc4b55ac1d79f1152a549ab9bfb170d2d Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:51:36 +0800
Subject: add standalone class for fcsr and senvcfg csr

---
 riscv/processor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 1c33911..5973baf 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -375,7 +375,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_FFLAGS] = fflags = std::make_shared<float_csr_t>(proc, CSR_FFLAGS, FSR_AEXC >> FSR_AEXC_SHIFT, 0);
   csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0);
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
-  csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
+  csrmap[CSR_FCSR] = std::make_shared<fcsr_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
 
   csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED);
 
@@ -390,7 +390,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MENVCFG] = menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
   const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
-  csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<masked_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
+  csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
   const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
-- 
cgit v1.1


From a3d112d6f29870249df1080c5c610291dbe94442 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 08:50:11 -0700
Subject: Remove mstatush mask as unnecessary

Mask in underlying CSR is sufficient.

Mask field in rv32_high_csr_t is now unneeded and will be removed next.
---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5973baf..febd61f 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -192,7 +192,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MSTATUS] = mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
 
   if (xlen == 32) {
-    const reg_t mstatush_mask = MSTATUSH_MPV | MSTATUSH_GVA | MSTATUSH_SBE | MSTATUSH_MBE;
+    const reg_t mstatush_mask = -1;
     csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatush_mask, mstatus);
   }
   csrmap[CSR_MEPC] = mepc = std::make_shared<epc_csr_t>(proc, CSR_MEPC);
-- 
cgit v1.1


From 00c38fdb95dff4e18ed75361da03436075a03b3a Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:01:15 -0700
Subject: Remove unnecessary mask from rv32_high_csr_t constructor

---
 riscv/processor.cc | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index febd61f..c0f4964 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -192,8 +192,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MSTATUS] = mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
 
   if (xlen == 32) {
-    const reg_t mstatush_mask = -1;
-    csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatush_mask, mstatus);
+    csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus);
   }
   csrmap[CSR_MEPC] = mepc = std::make_shared<epc_csr_t>(proc, CSR_MEPC);
   csrmap[CSR_MTVAL] = mtval = std::make_shared<basic_csr_t>(proc, CSR_MTVAL, 0);
@@ -405,13 +404,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
       const reg_t mstateen_mask = i == 0 ? mstateen0_mask : MSTATEEN_HSTATEEN;
       csrmap[CSR_MSTATEEN0 + i] = mstateen[i] = std::make_shared<masked_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen_mask, 0);
       if (xlen == 32) {
-        csrmap[CSR_MSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATEEN0H + i, -1, mstateen[i]);
+        csrmap[CSR_MSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATEEN0H + i, mstateen[i]);
       }
 
       const reg_t hstateen_mask = i == 0 ? hstateen0_mask : HSTATEEN_SSTATEEN;
       csrmap[CSR_HSTATEEN0 + i] = hstateen[i] = std::make_shared<hstateen_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen_mask, 0, i);
       if (xlen == 32) {
-        csrmap[CSR_HSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_HSTATEEN0H + i, -1, hstateen[i]);
+        csrmap[CSR_HSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_HSTATEEN0H + i, hstateen[i]);
       }
 
       const reg_t sstateen_mask = i == 0 ? sstateen0_mask : 0;
-- 
cgit v1.1


From 85ab2228ddb802c33a967349d69b2d948846bd01 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:33:36 -0700
Subject: Add proxy for accessing the low 32 bits of a 64-bit CSR

Use this for mstatus on RV32 so that `csrw mstatus` does not modify
the bits in `mstatush`. Fixes #1044.
---
 riscv/processor.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c0f4964..28129ba 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -189,10 +189,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   prv = PRV_M;
   v = false;
   csrmap[CSR_MISA] = misa = std::make_shared<misa_csr_t>(proc, CSR_MISA, max_isa);
-  csrmap[CSR_MSTATUS] = mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
+  mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS);
 
   if (xlen == 32) {
+    csrmap[CSR_MSTATUS] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATUS, mstatus);
     csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus);
+  } else {
+    csrmap[CSR_MSTATUS] = mstatus;
   }
   csrmap[CSR_MEPC] = mepc = std::make_shared<epc_csr_t>(proc, CSR_MEPC);
   csrmap[CSR_MTVAL] = mtval = std::make_shared<basic_csr_t>(proc, CSR_MTVAL, 0);
-- 
cgit v1.1


From f85b76edd00a529b3dbda88aee2802014c09de7d Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:48:23 -0700
Subject: Use rv32_low_csr_t for Smstateen CSRs

Otherwise they will have the same problem as #1044
---
 riscv/processor.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 28129ba..d431c68 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -405,15 +405,21 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     const reg_t mstateen0_mask = hstateen0_mask;
     for (int i = 0; i < 4; i++) {
       const reg_t mstateen_mask = i == 0 ? mstateen0_mask : MSTATEEN_HSTATEEN;
-      csrmap[CSR_MSTATEEN0 + i] = mstateen[i] = std::make_shared<masked_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen_mask, 0);
+      mstateen[i] = std::make_shared<masked_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen_mask, 0);
       if (xlen == 32) {
+        csrmap[CSR_MSTATEEN0 + i] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen[i]);
         csrmap[CSR_MSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATEEN0H + i, mstateen[i]);
+      } else {
+        csrmap[CSR_MSTATEEN0 + i] = mstateen[i];
       }
 
       const reg_t hstateen_mask = i == 0 ? hstateen0_mask : HSTATEEN_SSTATEEN;
-      csrmap[CSR_HSTATEEN0 + i] = hstateen[i] = std::make_shared<hstateen_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen_mask, 0, i);
+      hstateen[i] = std::make_shared<hstateen_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen_mask, 0, i);
       if (xlen == 32) {
+        csrmap[CSR_HSTATEEN0 + i] = std::make_shared<rv32_low_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen[i]);
         csrmap[CSR_HSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_HSTATEEN0H + i, hstateen[i]);
+      } else {
+        csrmap[CSR_HSTATEEN0 + i] = hstateen[i];
       }
 
       const reg_t sstateen_mask = i == 0 ? sstateen0_mask : 0;
-- 
cgit v1.1


From 3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 10:45:41 -0700
Subject: Properly log mstatush side effect updates

These have never been logged properly.
---
 riscv/processor.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index d431c68..8f77b47 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -193,7 +193,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
 
   if (xlen == 32) {
     csrmap[CSR_MSTATUS] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATUS, mstatus);
-    csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus);
+    csrmap[CSR_MSTATUSH] = mstatush = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus);
   } else {
     csrmap[CSR_MSTATUS] = mstatus;
   }
@@ -824,6 +824,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     s = set_field(s, MSTATUS_MPV, curr_virt);
     s = set_field(s, MSTATUS_GVA, t.has_gva());
     state.mstatus->write(s);
+    if (state.mstatush) state.mstatush->write(s >> 32);  // log mstatush change
     set_privilege(PRV_M);
   }
 }
-- 
cgit v1.1


From e8f5ce062b755a1c76eb02bc98adefbc64183cd3 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 20:48:09 +0800
Subject: add support for m/henvcfgh csrs

---
 riscv/processor.cc | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8f77b47..4b0b330 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -385,11 +385,18 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MIMPID] = std::make_shared<const_csr_t>(proc, CSR_MIMPID, 0);
   csrmap[CSR_MVENDORID] = std::make_shared<const_csr_t>(proc, CSR_MVENDORID, 0);
   csrmap[CSR_MHARTID] = std::make_shared<const_csr_t>(proc, CSR_MHARTID, proc->get_id());
+
   const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
                              (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
   const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
-  csrmap[CSR_MENVCFG] = menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
+  menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
+  if (xlen == 32) {
+    csrmap[CSR_MENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_MENVCFG, menvcfg);
+    csrmap[CSR_MENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MENVCFGH, menvcfg);
+  } else {
+    csrmap[CSR_MENVCFG] = menvcfg;
+  }
   const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
   csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
@@ -397,8 +404,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
                              (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
   const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
-  csrmap[CSR_HENVCFG] = henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
-
+  henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
+  if (xlen == 32) {
+    csrmap[CSR_HENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_HENVCFG, henvcfg);
+    csrmap[CSR_HENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HENVCFGH, henvcfg);
+  } else {
+    csrmap[CSR_HENVCFG] = henvcfg;
+  }
   if (proc->extension_enabled_const(EXT_SMSTATEEN)) {
     const reg_t sstateen0_mask = (proc->extension_enabled(EXT_ZFINX) ? SSTATEEN0_FCSR : 0) | SSTATEEN0_CS;
     const reg_t hstateen0_mask = sstateen0_mask | HSTATEEN0_SENVCFG | HSTATEEN_SSTATEEN;
-- 
cgit v1.1


From dd11aceaf6fb19c2e9ab549f1bcc3ae89ce1b735 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 20:53:55 +0800
Subject: add support for mconfigptr csr: it's hardwired to zero currently

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4b0b330..92f4b41 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -385,7 +385,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MIMPID] = std::make_shared<const_csr_t>(proc, CSR_MIMPID, 0);
   csrmap[CSR_MVENDORID] = std::make_shared<const_csr_t>(proc, CSR_MVENDORID, 0);
   csrmap[CSR_MHARTID] = std::make_shared<const_csr_t>(proc, CSR_MHARTID, proc->get_id());
-
+  csrmap[CSR_MCONFIGPTR] = std::make_shared<const_csr_t>(proc, CSR_MCONFIGPTR, 0);
   const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
                              (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
-- 
cgit v1.1


From d6f332d63aa5141cacd652cc5476e9d01ceb91e8 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Tue, 12 Jul 2022 23:21:01 +0800
Subject: add U mode check for *envcfg*

- If U-mode is not supported, then registers menvcfg and menvcfgh do not exist
- Since H extension requires S-mode, and S mode can not exsit without U-mode,
so senvcfg, henvcfg/henvcfgh also do not exist if U-mode is not supported
---
 riscv/processor.cc | 50 ++++++++++++++++++++++++++------------------------
 1 file changed, 26 insertions(+), 24 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 92f4b41..df82f9e 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -386,30 +386,32 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MVENDORID] = std::make_shared<const_csr_t>(proc, CSR_MVENDORID, 0);
   csrmap[CSR_MHARTID] = std::make_shared<const_csr_t>(proc, CSR_MHARTID, proc->get_id());
   csrmap[CSR_MCONFIGPTR] = std::make_shared<const_csr_t>(proc, CSR_MCONFIGPTR, 0);
-  const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
-                             (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
-                             (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
-  const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
-  menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
-  if (xlen == 32) {
-    csrmap[CSR_MENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_MENVCFG, menvcfg);
-    csrmap[CSR_MENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MENVCFGH, menvcfg);
-  } else {
-    csrmap[CSR_MENVCFG] = menvcfg;
-  }
-  const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
-                             (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
-  csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
-  const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
-                             (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
-                             (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
-  const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
-  henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
-  if (xlen == 32) {
-    csrmap[CSR_HENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_HENVCFG, henvcfg);
-    csrmap[CSR_HENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HENVCFGH, henvcfg);
-  } else {
-    csrmap[CSR_HENVCFG] = henvcfg;
+  if (proc->extension_enabled_const('U')) {
+    const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
+                              (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
+                              (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
+    const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
+    menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
+    if (xlen == 32) {
+      csrmap[CSR_MENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_MENVCFG, menvcfg);
+      csrmap[CSR_MENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MENVCFGH, menvcfg);
+    } else {
+      csrmap[CSR_MENVCFG] = menvcfg;
+    }
+    const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
+                              (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
+    csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
+    const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
+                              (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
+                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
+    const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
+    henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
+    if (xlen == 32) {
+      csrmap[CSR_HENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_HENVCFG, henvcfg);
+      csrmap[CSR_HENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HENVCFGH, henvcfg);
+    } else {
+      csrmap[CSR_HENVCFG] = henvcfg;
+    }
   }
   if (proc->extension_enabled_const(EXT_SMSTATEEN)) {
     const reg_t sstateen0_mask = (proc->extension_enabled(EXT_ZFINX) ? SSTATEEN0_FCSR : 0) | SSTATEEN0_CS;
-- 
cgit v1.1


From 28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 18:34:13 +0800
Subject: modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t

---
 riscv/processor.cc | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8f77b47..c351d1d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -202,20 +202,25 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MSCRATCH] = std::make_shared<basic_csr_t>(proc, CSR_MSCRATCH, 0);
   csrmap[CSR_MTVEC] = mtvec = std::make_shared<tvec_csr_t>(proc, CSR_MTVEC);
   csrmap[CSR_MCAUSE] = mcause = std::make_shared<cause_csr_t>(proc, CSR_MCAUSE);
-  csrmap[CSR_MINSTRET] = minstret = std::make_shared<wide_counter_csr_t>(proc, CSR_MINSTRET);
-  csrmap[CSR_MCYCLE] = mcycle = std::make_shared<wide_counter_csr_t>(proc, CSR_MCYCLE);
+  minstret = std::make_shared<wide_counter_csr_t>(proc, CSR_MINSTRET);
+  mcycle = std::make_shared<wide_counter_csr_t>(proc, CSR_MCYCLE);
   if (proc->extension_enabled_const(EXT_ZICNTR)) {
     csrmap[CSR_INSTRET] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRET, minstret);
     csrmap[CSR_CYCLE] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLE, mcycle);
   }
   if (xlen == 32) {
-    counter_top_csr_t_p minstreth, mcycleh;
-    csrmap[CSR_MINSTRETH] = minstreth = std::make_shared<counter_top_csr_t>(proc, CSR_MINSTRETH, minstret);
-    csrmap[CSR_MCYCLEH] = mcycleh = std::make_shared<counter_top_csr_t>(proc, CSR_MCYCLEH, mcycle);
+    csr_t_p minstreth, mcycleh;
+    csrmap[CSR_MINSTRET] = std::make_shared<rv32_low_csr_t>(proc, CSR_MINSTRET, minstret);
+    csrmap[CSR_MINSTRETH] = minstreth = std::make_shared<rv32_high_csr_t>(proc, CSR_MINSTRETH, minstret);
+    csrmap[CSR_MCYCLE] = std::make_shared<rv32_low_csr_t>(proc, CSR_MCYCLE, mcycle);
+    csrmap[CSR_MCYCLEH] = mcycleh = std::make_shared<rv32_high_csr_t>(proc, CSR_MCYCLEH, mcycle);
     if (proc->extension_enabled_const(EXT_ZICNTR)) {
       csrmap[CSR_INSTRETH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRETH, minstreth);
       csrmap[CSR_CYCLEH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLEH, mcycleh);
     }
+  } else {
+    csrmap[CSR_MINSTRET] = minstret;
+    csrmap[CSR_MCYCLE] = mcycle;
   }
   for (reg_t i = 3; i <= 31; ++i) {
     const reg_t which_mevent = CSR_MHPMEVENT3 + i - 3;
-- 
cgit v1.1


From 3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 20:30:02 +0800
Subject: add support for time/timeh/htimedelta/htimedeltah csrs

---
 riscv/processor.cc | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c351d1d..642f1fb 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -204,9 +204,11 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MCAUSE] = mcause = std::make_shared<cause_csr_t>(proc, CSR_MCAUSE);
   minstret = std::make_shared<wide_counter_csr_t>(proc, CSR_MINSTRET);
   mcycle = std::make_shared<wide_counter_csr_t>(proc, CSR_MCYCLE);
+  time = std::make_shared<time_counter_csr_t>(proc, CSR_TIME);
   if (proc->extension_enabled_const(EXT_ZICNTR)) {
     csrmap[CSR_INSTRET] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRET, minstret);
     csrmap[CSR_CYCLE] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLE, mcycle);
+    csrmap[CSR_TIME] = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIME, time);
   }
   if (xlen == 32) {
     csr_t_p minstreth, mcycleh;
@@ -215,8 +217,10 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     csrmap[CSR_MCYCLE] = std::make_shared<rv32_low_csr_t>(proc, CSR_MCYCLE, mcycle);
     csrmap[CSR_MCYCLEH] = mcycleh = std::make_shared<rv32_high_csr_t>(proc, CSR_MCYCLEH, mcycle);
     if (proc->extension_enabled_const(EXT_ZICNTR)) {
+      auto timeh = std::make_shared<rv32_high_csr_t>(proc, CSR_TIMEH, time);
       csrmap[CSR_INSTRETH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRETH, minstreth);
       csrmap[CSR_CYCLEH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLEH, mcycleh);
+      csrmap[CSR_TIMEH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIMEH, timeh);
     }
   } else {
     csrmap[CSR_MINSTRET] = minstret;
@@ -349,6 +353,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     (1 << CAUSE_STORE_PAGE_FAULT);
   csrmap[CSR_HEDELEG] = hedeleg = std::make_shared<masked_csr_t>(proc, CSR_HEDELEG, hedeleg_mask, 0);
   csrmap[CSR_HCOUNTEREN] = hcounteren = std::make_shared<masked_csr_t>(proc, CSR_HCOUNTEREN, counteren_mask, 0);
+  htimedelta = std::make_shared<basic_csr_t>(proc, CSR_HTIMEDELTA, 0);
+  if (xlen == 32) {
+    csrmap[CSR_HTIMEDELTA] = std::make_shared<rv32_low_csr_t>(proc, CSR_HTIMEDELTA, htimedelta);
+    csrmap[CSR_HTIMEDELTAH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HTIMEDELTAH, htimedelta);
+  } else {
+    csrmap[CSR_HTIMEDELTA] = htimedelta;
+  }
   csrmap[CSR_HTVAL] = htval = std::make_shared<basic_csr_t>(proc, CSR_HTVAL, 0);
   csrmap[CSR_HTINST] = htinst = std::make_shared<basic_csr_t>(proc, CSR_HTINST, 0);
   csrmap[CSR_HGATP] = hgatp = std::make_shared<hgatp_csr_t>(proc, CSR_HGATP);
-- 
cgit v1.1


From eb2cce0c99075f89e77b0c1db92108f9c49ccab0 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 3 Aug 2022 10:32:51 +0800
Subject: add stateen related check to frm/fflags and then apply to fcsr
 implicitly

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6d0d349..ddb0344 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -393,7 +393,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_FFLAGS] = fflags = std::make_shared<float_csr_t>(proc, CSR_FFLAGS, FSR_AEXC >> FSR_AEXC_SHIFT, 0);
   csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0);
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
-  csrmap[CSR_FCSR] = std::make_shared<fcsr_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
+  csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
 
   csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED);
 
-- 
cgit v1.1


From 5672c4a41ad7a9af011d385962c175a5a6012fd9 Mon Sep 17 00:00:00 2001
From: i2h2 <110197402+i2h2@users.noreply.github.com>
Date: Wed, 3 Aug 2022 16:01:57 -0600
Subject: Add Sstc support. (#1057)

---
 riscv/processor.cc | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6d0d349..0389707 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -208,7 +208,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   if (proc->extension_enabled_const(EXT_ZICNTR)) {
     csrmap[CSR_INSTRET] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRET, minstret);
     csrmap[CSR_CYCLE] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLE, mcycle);
-    csrmap[CSR_TIME] = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIME, time);
+    csrmap[CSR_TIME] = time_proxy = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIME, time);
   }
   if (xlen == 32) {
     csr_t_p minstreth, mcycleh;
@@ -405,7 +405,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   if (proc->extension_enabled_const('U')) {
     const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) |
                               (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) |
-                              (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
+                              (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) |
+                              (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0);
     const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0);
     menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
     if (xlen == 32) {
@@ -419,7 +420,8 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
     const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
                               (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
-                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
+                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) |
+                              (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0);
     const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);
     henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg);
     if (xlen == 32) {
@@ -457,6 +459,21 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
     }
   }
 
+  if (proc->extension_enabled_const(EXT_SSTC)) {
+    stimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_STIMECMP, MIP_STIP);
+    vstimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_VSTIMECMP, MIP_VSTIP);
+    auto virtualized_stimecmp = std::make_shared<virtualized_stimecmp_csr_t>(proc, stimecmp, vstimecmp);
+    if (xlen == 32) {
+      csrmap[CSR_STIMECMP] = std::make_shared<rv32_low_csr_t>(proc, CSR_STIMECMP, virtualized_stimecmp);
+      csrmap[CSR_STIMECMPH] = std::make_shared<rv32_high_csr_t>(proc, CSR_STIMECMPH, virtualized_stimecmp);
+      csrmap[CSR_VSTIMECMP] = std::make_shared<rv32_low_csr_t>(proc, CSR_VSTIMECMP, vstimecmp);
+      csrmap[CSR_VSTIMECMPH] = std::make_shared<rv32_high_csr_t>(proc, CSR_VSTIMECMPH, vstimecmp);
+    } else {
+      csrmap[CSR_STIMECMP] = virtualized_stimecmp;
+      csrmap[CSR_VSTIMECMP] = vstimecmp;
+    }
+  }
+
   serialized = false;
 
 #ifdef RISCV_ENABLE_COMMITLOG
-- 
cgit v1.1


From ba10686fd18f3fbb036ca04b906deb57e7d1fe54 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Mon, 4 Jul 2022 21:31:09 +0800
Subject: add support for sscofpmf extension v0.5.2

since spike doesn't truly support counting of hardware performance events,
only csr related read/write functions is supported currently
---
 riscv/processor.cc | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0389707..7cac387 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -228,13 +228,15 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   }
   for (reg_t i = 3; i <= 31; ++i) {
     const reg_t which_mevent = CSR_MHPMEVENT3 + i - 3;
+    const reg_t which_meventh = CSR_MHPMEVENT3H + i - 3;
     const reg_t which_mcounter = CSR_MHPMCOUNTER3 + i - 3;
     const reg_t which_mcounterh = CSR_MHPMCOUNTER3H + i - 3;
     const reg_t which_counter = CSR_HPMCOUNTER3 + i - 3;
     const reg_t which_counterh = CSR_HPMCOUNTER3H + i - 3;
-    auto mevent = std::make_shared<const_csr_t>(proc, which_mevent, 0);
+    const reg_t mevent_mask = proc->extension_enabled_const(EXT_SSCOFPMF) ? MHPMEVENT_VUINH | MHPMEVENT_VSINH | MHPMEVENTH_UINH |
+                                                                            MHPMEVENT_UINH | MHPMEVENT_MINH | MHPMEVENT_OF : 0;
+    mevent[i - 3] = std::make_shared<masked_csr_t>(proc, which_mevent, mevent_mask, 0);
     auto mcounter = std::make_shared<const_csr_t>(proc, which_mcounter, 0);
-    csrmap[which_mevent] = mevent;
     csrmap[which_mcounter] = mcounter;
 
     if (proc->extension_enabled_const(EXT_ZICNTR) && proc->extension_enabled_const(EXT_ZIHPM)) {
@@ -242,21 +244,30 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
       csrmap[which_counter] = counter;
     }
     if (xlen == 32) {
+      csrmap[which_mevent] = std::make_shared<rv32_low_csr_t>(proc, which_mevent, mevent[i - 3]);;
       auto mcounterh = std::make_shared<const_csr_t>(proc, which_mcounterh, 0);
       csrmap[which_mcounterh] = mcounterh;
       if (proc->extension_enabled_const(EXT_ZICNTR) && proc->extension_enabled_const(EXT_ZIHPM)) {
         auto counterh = std::make_shared<counter_proxy_csr_t>(proc, which_counterh, mcounterh);
         csrmap[which_counterh] = counterh;
       }
+      if (proc->extension_enabled_const(EXT_SSCOFPMF)) {
+        auto meventh = std::make_shared<rv32_high_csr_t>(proc, which_meventh, mevent[i - 3]);
+        csrmap[which_meventh] = meventh;
+      }
+    } else {
+      csrmap[which_mevent] = mevent[i - 3];
     }
   }
   csrmap[CSR_MCOUNTINHIBIT] = std::make_shared<const_csr_t>(proc, CSR_MCOUNTINHIBIT, 0);
+  if (proc->extension_enabled_const(EXT_SSCOFPMF))
+    csrmap[CSR_SCOUNTOVF] = std::make_shared<scountovf_csr_t>(proc, CSR_SCOUNTOVF);
   csrmap[CSR_MIE] = mie = std::make_shared<mie_csr_t>(proc, CSR_MIE);
   csrmap[CSR_MIP] = mip = std::make_shared<mip_csr_t>(proc, CSR_MIP);
   auto sip_sie_accr = std::make_shared<generic_int_accessor_t>(
     this,
     ~MIP_HS_MASK,  // read_mask
-    MIP_SSIP,      // ip_write_mask
+    MIP_SSIP | MIP_LCOFIP,  // ip_write_mask
     ~MIP_HS_MASK,  // ie_write_mask
     generic_int_accessor_t::mask_mode_t::MIDELEG,
     0              // shiftamt
-- 
cgit v1.1


From 6cca5ec9c566301f8e85f83c4505e53b1ffe9249 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Tue, 5 Jul 2022 17:21:09 +0800
Subject: modify take_interrupt to support LCOFIP irq

---
 riscv/processor.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7cac387..164ecff 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -716,6 +716,8 @@ void processor_t::take_interrupt(reg_t pending_interrupts)
       enabled_interrupts = MIP_SSIP;
     else if (enabled_interrupts & MIP_STIP)
       enabled_interrupts = MIP_STIP;
+    else if (enabled_interrupts & MIP_LCOFIP)
+      enabled_interrupts = MIP_LCOFIP;
     else if (enabled_interrupts & MIP_VSEIP)
       enabled_interrupts = MIP_VSEIP;
     else if (enabled_interrupts & MIP_VSSIP)
-- 
cgit v1.1


From 793ffe508a5b81ce27f1baf2c5afb0b58a4236c6 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Sun, 31 Jul 2022 20:39:47 +0800
Subject: Fix code indentation in processor.cc, interactive.cc,
 debug_module.h/cc execute.cc, entropy_source.h and v_ext_macros.h

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0325c51..790f18c 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -588,7 +588,7 @@ void processor_t::reset()
     put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
   }
 
-   for (auto e : custom_extensions) // reset any extensions
+  for (auto e : custom_extensions) // reset any extensions
     e.second->reset();
 
   if (sim)
-- 
cgit v1.1


From 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 10 Aug 2022 11:02:23 +0800
Subject: Improve write log for vtype in set_vl

Two writes to vtype will be logged in commitlog if vill is true
---
 riscv/processor.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 790f18c..620a6f4 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -512,7 +512,6 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
 {
   int new_vlmul = 0;
   if (vtype->read() != newType) {
-    vtype->write_raw(newType);
     vsew = 1 << (extract64(newType, 3, 3) + 3);
     new_vlmul = int8_t(extract64(newType, 0, 3) << 5) >> 5;
     vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul);
@@ -527,6 +526,8 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT
     if (vill) {
       vlmax = 0;
       vtype->write_raw(UINT64_MAX << (p->get_xlen() - 1));
+    } else {
+      vtype->write_raw(newType);
     }
   }
 
-- 
cgit v1.1


From 3ac734e195e76e7c5e52448a95ea91885af31647 Mon Sep 17 00:00:00 2001
From: YenHaoChen <howard25336284@gmail.com>
Date: Thu, 25 Aug 2022 20:47:15 +0800
Subject: Fix tval on illegal instruction faults with long illegal instruction

The current spike implementation does not include the ILEN (maximum
instruction length supported by the implementation), which is required
to constrain the value of tval on an illegal instruction exception.

Consider an implementation supporting only an RV64I base instruction
set. The ILEN is 32 bits (spec sec. 1.5), and the MXLEN is 64 bits (spec
sec. 5.1). Under an illegal instruction exception with the instruction
longer than the ILEN, the mtval should contain the first ILEN (32 bits)
of the faulting instruction. However, the current spike implementation
lets the mtval be the instruction's first MXLEN (64 bits).

To fix this bug, this PR masks out the upper bits of the tval and leaves
the first ILEN bits of the faulting instruction. When this PR is being
made, all official instructions are either 16 or 32 bits. So, We hard-
code the ILEN to 32 bits.
---
 riscv/processor.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 620a6f4..3d56abc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -949,7 +949,10 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 {
-  throw trap_illegal_instruction(insn.bits());
+  // The illegal instruction can be longer than ILEN bits, where the tval will
+  // contain the first ILEN bits of the faulting instruction. We hard-code the
+  // ILEN to 32 bits since all official instructions have at most 32 bits.
+  throw trap_illegal_instruction(insn.bits() & 0xffffffffULL);
 }
 
 insn_func_t processor_t::decode_insn(insn_t insn)
-- 
cgit v1.1


From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 22 Sep 2022 17:34:33 -0700
Subject: Suppress most unused variable warnings

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5ae6bbb..9bb7d04 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -960,7 +960,7 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
   throw trap_illegal_instruction(insn.bits());
 }
 
-reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
+reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc)
 {
   // The illegal instruction can be longer than ILEN bits, where the tval will
   // contain the first ILEN bits of the faulting instruction. We hard-code the
-- 
cgit v1.1


From 3ee74b7be334d1e2393a134f26de8dfe0cd65feb Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 22 Sep 2022 18:01:19 -0700
Subject: Silence unused-variable warnings in auto-generated code

---
 riscv/processor.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'riscv/processor.cc')

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9bb7d04..217d49d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -20,6 +20,10 @@
 #include <string>
 #include <algorithm>
 
+#ifdef __GNUC__
+# pragma GCC diagnostic ignored "-Wunused-variable"
+#endif
+
 #undef STATE
 #define STATE state
 
-- 
cgit v1.1