From 80be4e21c3af7fe2966788ce538d3e3c3b0d60e3 Mon Sep 17 00:00:00 2001
From: Dan Lustig <dlustig@nvidia.com>
Date: Thu, 22 Jul 2021 07:36:18 -0400
Subject: Non-leaf PTEs with D/A/U==1 are reserved

...and hence should trigger page faults

Thanks to @pdonahue-ventana for pointing this out:
https://github.com/riscv/riscv-tests/issues/352
---
 riscv/mmu.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'riscv/mmu.cc')

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index bc2dcc8..fe96870 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -415,6 +415,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool mxr)
     if (pte & PTE_RSVD) {
       break;
     } else if (PTE_TABLE(pte)) { // next level of page table
+      if (pte & (PTE_D | PTE_A | PTE_U))
+        break;
       base = ppn << PGSHIFT;
     } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) {
       break;
-- 
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