From a0298a33e7b2091ba8d9f3a20838d96dc1164cac Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 19 May 2022 17:11:07 -0700 Subject: Move ebreak* logic from take_trap into instructions. (#1006) Now that logic only affects ebreak instructions, and does not affect triggers that also cause a trap to be taken. Fixes #725. Although like Paul, I don't have a test for this case. Introduce trap_debug_mode so so ebreak instructions can force entry into debug mode. --- riscv/insns/c_ebreak.h | 9 ++++++++- riscv/insns/ebreak.h | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h index 7d04f46..c8cc1f5 100644 --- a/riscv/insns/c_ebreak.h +++ b/riscv/insns/c_ebreak.h @@ -1,2 +1,9 @@ require_extension('C'); -throw trap_breakpoint(STATE.v, pc); +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h index 9f3d44d..227ab93 100644 --- a/riscv/insns/ebreak.h +++ b/riscv/insns/ebreak.h @@ -1 +1,8 @@ -throw trap_breakpoint(STATE.v, pc); +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} -- cgit v1.1 From 66fd65c0d2ebc84bd8d8f82258e0988fdca07719 Mon Sep 17 00:00:00 2001 From: ChunPing Chung Date: Fri, 29 Jul 2022 03:01:26 +0800 Subject: Fix overflow issue of p-ext multiply instructions (#1053) --- riscv/insns/smul16.h | 2 +- riscv/insns/smul8.h | 2 +- riscv/insns/smulx16.h | 2 +- riscv/insns/smulx8.h | 2 +- riscv/insns/umul16.h | 2 +- riscv/insns/umul8.h | 2 +- riscv/insns/umulx16.h | 2 +- riscv/insns/umulx8.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/smul16.h b/riscv/insns/smul16.h index 8f87612..7e0f08a 100644 --- a/riscv/insns/smul16.h +++ b/riscv/insns/smul16.h @@ -1,3 +1,3 @@ P_MUL_LOOP(16, { - pd = ps1 * ps2; + pd = (int32_t)ps1 * (int32_t)ps2; }) diff --git a/riscv/insns/smul8.h b/riscv/insns/smul8.h index 155e50e..a4a3ed9 100644 --- a/riscv/insns/smul8.h +++ b/riscv/insns/smul8.h @@ -1,3 +1,3 @@ P_MUL_LOOP(8, { - pd = ps1 * ps2; + pd = (int16_t)ps1 * (int16_t)ps2; }) diff --git a/riscv/insns/smulx16.h b/riscv/insns/smulx16.h index 14ae047..58e9a08 100644 --- a/riscv/insns/smulx16.h +++ b/riscv/insns/smulx16.h @@ -1,3 +1,3 @@ P_MUL_CROSS_LOOP(16, { - pd = ps1 * ps2; + pd = (int32_t)ps1 * (int32_t)ps2; }) diff --git a/riscv/insns/smulx8.h b/riscv/insns/smulx8.h index b5ae41c..9270ce3 100644 --- a/riscv/insns/smulx8.h +++ b/riscv/insns/smulx8.h @@ -1,3 +1,3 @@ P_MUL_CROSS_LOOP(8, { - pd = ps1 * ps2; + pd = (int16_t)ps1 * (int16_t)ps2; }) diff --git a/riscv/insns/umul16.h b/riscv/insns/umul16.h index 860f942..09b839c 100644 --- a/riscv/insns/umul16.h +++ b/riscv/insns/umul16.h @@ -1,3 +1,3 @@ P_MUL_ULOOP(16, { - pd = ps1 * ps2; + pd = (uint32_t)ps1 * (uint32_t)ps2; }) diff --git a/riscv/insns/umul8.h b/riscv/insns/umul8.h index 04d7a6e..29cae88 100644 --- a/riscv/insns/umul8.h +++ b/riscv/insns/umul8.h @@ -1,3 +1,3 @@ P_MUL_ULOOP(8, { - pd = ps1 * ps2; + pd = (uint16_t)ps1 * (uint16_t)ps2; }) diff --git a/riscv/insns/umulx16.h b/riscv/insns/umulx16.h index 5abe9cf..3f0cce8 100644 --- a/riscv/insns/umulx16.h +++ b/riscv/insns/umulx16.h @@ -1,3 +1,3 @@ P_MUL_CROSS_ULOOP(16, { - pd = ps1 * ps2; + pd = (uint32_t)ps1 * (uint32_t)ps2; }) diff --git a/riscv/insns/umulx8.h b/riscv/insns/umulx8.h index a2b073d..848b5d5 100644 --- a/riscv/insns/umulx8.h +++ b/riscv/insns/umulx8.h @@ -1,3 +1,3 @@ P_MUL_CROSS_ULOOP(8, { - pd = ps1 * ps2; + pd = (uint16_t)ps1 * (uint16_t)ps2; }) -- cgit v1.1 From 2d69ec069e6e771eaf59b419b2bfd89d5298c53c Mon Sep 17 00:00:00 2001 From: Canberk Topal Date: Tue, 26 Jul 2022 16:26:39 +0100 Subject: WFI condition fix Before this commit Spike was requiring S mode privilege even without S mode implemented. This commit fixes it. Signed-off-by: Canberk Topal --- riscv/insns/wfi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'riscv/insns') diff --git a/riscv/insns/wfi.h b/riscv/insns/wfi.h index 299cb01..3411da0 100644 --- a/riscv/insns/wfi.h +++ b/riscv/insns/wfi.h @@ -5,7 +5,9 @@ if (STATE.v && STATE.prv == PRV_U) { } else if (STATE.v) { // VS-mode if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) require_novirt(); -} else { +} else if (p->extension_enabled('S')) { + // When S-mode is implemented, then executing WFI in + // U-mode causes an illegal instruction exception. require_privilege(PRV_S); } wfi(); -- cgit v1.1 From 5de0c89c034cf64fdab8e36d2dc7488aa035d823 Mon Sep 17 00:00:00 2001 From: liweiwei Date: Thu, 14 Oct 2021 09:49:10 +0800 Subject: Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng --- riscv/insns/fadd_d.h | 4 ++-- riscv/insns/fadd_h.h | 4 ++-- riscv/insns/fadd_s.h | 4 ++-- riscv/insns/fclass_d.h | 4 ++-- riscv/insns/fclass_h.h | 4 ++-- riscv/insns/fclass_s.h | 4 ++-- riscv/insns/fcvt_d_h.h | 6 +++--- riscv/insns/fcvt_d_l.h | 4 ++-- riscv/insns/fcvt_d_lu.h | 4 ++-- riscv/insns/fcvt_d_s.h | 4 ++-- riscv/insns/fcvt_d_w.h | 4 ++-- riscv/insns/fcvt_d_wu.h | 4 ++-- riscv/insns/fcvt_h_d.h | 6 +++--- riscv/insns/fcvt_h_l.h | 4 ++-- riscv/insns/fcvt_h_lu.h | 4 ++-- riscv/insns/fcvt_h_s.h | 4 ++-- riscv/insns/fcvt_h_w.h | 4 ++-- riscv/insns/fcvt_h_wu.h | 4 ++-- riscv/insns/fcvt_l_d.h | 4 ++-- riscv/insns/fcvt_l_h.h | 4 ++-- riscv/insns/fcvt_l_s.h | 4 ++-- riscv/insns/fcvt_lu_d.h | 4 ++-- riscv/insns/fcvt_lu_h.h | 4 ++-- riscv/insns/fcvt_lu_s.h | 4 ++-- riscv/insns/fcvt_s_d.h | 4 ++-- riscv/insns/fcvt_s_h.h | 4 ++-- riscv/insns/fcvt_s_l.h | 4 ++-- riscv/insns/fcvt_s_lu.h | 4 ++-- riscv/insns/fcvt_s_w.h | 4 ++-- riscv/insns/fcvt_s_wu.h | 4 ++-- riscv/insns/fcvt_w_d.h | 4 ++-- riscv/insns/fcvt_w_h.h | 4 ++-- riscv/insns/fcvt_w_s.h | 4 ++-- riscv/insns/fcvt_wu_d.h | 4 ++-- riscv/insns/fcvt_wu_h.h | 4 ++-- riscv/insns/fcvt_wu_s.h | 4 ++-- riscv/insns/fdiv_d.h | 4 ++-- riscv/insns/fdiv_h.h | 4 ++-- riscv/insns/fdiv_s.h | 4 ++-- riscv/insns/feq_d.h | 4 ++-- riscv/insns/feq_h.h | 4 ++-- riscv/insns/feq_s.h | 4 ++-- riscv/insns/fle_d.h | 4 ++-- riscv/insns/fle_h.h | 4 ++-- riscv/insns/fle_s.h | 4 ++-- riscv/insns/flt_d.h | 4 ++-- riscv/insns/flt_h.h | 4 ++-- riscv/insns/flt_s.h | 4 ++-- riscv/insns/fmadd_d.h | 4 ++-- riscv/insns/fmadd_h.h | 4 ++-- riscv/insns/fmadd_s.h | 4 ++-- riscv/insns/fmax_d.h | 12 ++++++------ riscv/insns/fmax_h.h | 4 ++-- riscv/insns/fmax_s.h | 12 ++++++------ riscv/insns/fmin_d.h | 12 ++++++------ riscv/insns/fmin_h.h | 4 ++-- riscv/insns/fmin_s.h | 12 ++++++------ riscv/insns/fmsub_d.h | 4 ++-- riscv/insns/fmsub_h.h | 4 ++-- riscv/insns/fmsub_s.h | 4 ++-- riscv/insns/fmul_d.h | 4 ++-- riscv/insns/fmul_h.h | 4 ++-- riscv/insns/fmul_s.h | 4 ++-- riscv/insns/fnmadd_d.h | 4 ++-- riscv/insns/fnmadd_h.h | 4 ++-- riscv/insns/fnmadd_s.h | 4 ++-- riscv/insns/fnmsub_d.h | 4 ++-- riscv/insns/fnmsub_h.h | 4 ++-- riscv/insns/fnmsub_s.h | 4 ++-- riscv/insns/fsgnj_d.h | 4 ++-- riscv/insns/fsgnj_h.h | 4 ++-- riscv/insns/fsgnj_s.h | 4 ++-- riscv/insns/fsgnjn_d.h | 4 ++-- riscv/insns/fsgnjn_h.h | 4 ++-- riscv/insns/fsgnjn_q.h | 2 +- riscv/insns/fsgnjn_s.h | 4 ++-- riscv/insns/fsgnjx_d.h | 4 ++-- riscv/insns/fsgnjx_h.h | 4 ++-- riscv/insns/fsgnjx_s.h | 4 ++-- riscv/insns/fsqrt_d.h | 4 ++-- riscv/insns/fsqrt_h.h | 4 ++-- riscv/insns/fsqrt_s.h | 4 ++-- riscv/insns/fsub_d.h | 4 ++-- riscv/insns/fsub_h.h | 4 ++-- riscv/insns/fsub_s.h | 4 ++-- riscv/insns/vfslide1down_vf.h | 6 +++--- riscv/insns/vfslide1up_vf.h | 6 +++--- 87 files changed, 193 insertions(+), 193 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h index 4a436e2..9bfff5f 100644 --- a/riscv/insns/fadd_d.h +++ b/riscv/insns/fadd_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_add(f64(FRS1), f64(FRS2))); +WRITE_FRD_D(f64_add(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h index 2b646ae..f57e5fa 100644 --- a/riscv/insns/fadd_h.h +++ b/riscv/insns/fadd_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_add(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_add(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h index cc18d58..7a40b1b 100644 --- a/riscv/insns/fadd_s.h +++ b/riscv/insns/fadd_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_add(f32(FRS1), f32(FRS2))); +WRITE_FRD_F(f32_add(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h index 9456123..a355062 100644 --- a/riscv/insns/fclass_d.h +++ b/riscv/insns/fclass_d.h @@ -1,3 +1,3 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_RD(f64_classify(f64(FRS1))); +WRITE_RD(f64_classify(FRS1_D)); diff --git a/riscv/insns/fclass_h.h b/riscv/insns/fclass_h.h index 066a2d2..2638ac8 100644 --- a/riscv/insns/fclass_h.h +++ b/riscv/insns/fclass_h.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_RD(f16_classify(f16(FRS1))); +WRITE_RD(f16_classify(FRS1_H)); diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h index a392db8..3d529ad 100644 --- a/riscv/insns/fclass_s.h +++ b/riscv/insns/fclass_s.h @@ -1,3 +1,3 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_RD(f32_classify(f32(FRS1))); +WRITE_RD(f32_classify(FRS1_F)); diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h index 04e9ff4..061a271 100644 --- a/riscv/insns/fcvt_d_h.h +++ b/riscv/insns/fcvt_d_h.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFHMIN); -require_extension('D'); +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_to_f64(f16(FRS1))); +WRITE_FRD_D(f16_to_f64(FRS1_H)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h index 08716cf..7788f1f 100644 --- a/riscv/insns/fcvt_d_l.h +++ b/riscv/insns/fcvt_d_l.h @@ -1,6 +1,6 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i64_to_f64(RS1)); +WRITE_FRD_D(i64_to_f64(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h index 306d7fe..edb694f 100644 --- a/riscv/insns/fcvt_d_lu.h +++ b/riscv/insns/fcvt_d_lu.h @@ -1,6 +1,6 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui64_to_f64(RS1)); +WRITE_FRD_D(ui64_to_f64(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h index 5f805b0..8039e94 100644 --- a/riscv/insns/fcvt_d_s.h +++ b/riscv/insns/fcvt_d_s.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_to_f64(f32(FRS1))); +WRITE_FRD_D(f32_to_f64(FRS1_F)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h index 4c4861c..e3375fa 100644 --- a/riscv/insns/fcvt_d_w.h +++ b/riscv/insns/fcvt_d_w.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i32_to_f64((int32_t)RS1)); +WRITE_FRD_D(i32_to_f64((int32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h index 1dbf218..d903561 100644 --- a/riscv/insns/fcvt_d_wu.h +++ b/riscv/insns/fcvt_d_wu.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f64((uint32_t)RS1)); +WRITE_FRD_D(ui32_to_f64((uint32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h index e9987b7..e06b1a5 100644 --- a/riscv/insns/fcvt_h_d.h +++ b/riscv/insns/fcvt_h_d.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFHMIN); -require_extension('D'); +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_to_f16(f64(FRS1))); +WRITE_FRD_H(f64_to_f16(FRS1_D)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h index 39178c2..31e8a1e 100644 --- a/riscv/insns/fcvt_h_l.h +++ b/riscv/insns/fcvt_h_l.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i64_to_f16(RS1)); +WRITE_FRD_H(i64_to_f16(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h index a872c48..189b160 100644 --- a/riscv/insns/fcvt_h_lu.h +++ b/riscv/insns/fcvt_h_lu.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui64_to_f16(RS1)); +WRITE_FRD_H(ui64_to_f16(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h index ce39d81..57ba005 100644 --- a/riscv/insns/fcvt_h_s.h +++ b/riscv/insns/fcvt_h_s.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFHMIN); +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_to_f16(f32(FRS1))); +WRITE_FRD_H(f32_to_f16(FRS1_F)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h index c082454..de4cbe5 100644 --- a/riscv/insns/fcvt_h_w.h +++ b/riscv/insns/fcvt_h_w.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i32_to_f16((int32_t)RS1)); +WRITE_FRD_H(i32_to_f16((int32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h index 9f2f5f6..230c354 100644 --- a/riscv/insns/fcvt_h_wu.h +++ b/riscv/insns/fcvt_h_wu.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f16((uint32_t)RS1)); +WRITE_FRD_H(ui32_to_f16((uint32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h index c09e6c4..f2374d2 100644 --- a/riscv/insns/fcvt_l_d.h +++ b/riscv/insns/fcvt_l_d.h @@ -1,6 +1,6 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f64_to_i64(f64(FRS1), RM, true)); +WRITE_RD(f64_to_i64(FRS1_D, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h index 5a1fea8..3b63027 100644 --- a/riscv/insns/fcvt_l_h.h +++ b/riscv/insns/fcvt_l_h.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f16_to_i64(f16(FRS1), RM, true)); +WRITE_RD(f16_to_i64(FRS1_H, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h index 267e0eb..d121a65 100644 --- a/riscv/insns/fcvt_l_s.h +++ b/riscv/insns/fcvt_l_s.h @@ -1,6 +1,6 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f32_to_i64(f32(FRS1), RM, true)); +WRITE_RD(f32_to_i64(FRS1_F, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h index 3a02120..939bc0e 100644 --- a/riscv/insns/fcvt_lu_d.h +++ b/riscv/insns/fcvt_lu_d.h @@ -1,6 +1,6 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f64_to_ui64(f64(FRS1), RM, true)); +WRITE_RD(f64_to_ui64(FRS1_D, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h index f1454c3..d27f175 100644 --- a/riscv/insns/fcvt_lu_h.h +++ b/riscv/insns/fcvt_lu_h.h @@ -1,6 +1,6 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f16_to_ui64(f16(FRS1), RM, true)); +WRITE_RD(f16_to_ui64(FRS1_H, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h index 94115a3..69c95ef 100644 --- a/riscv/insns/fcvt_lu_s.h +++ b/riscv/insns/fcvt_lu_s.h @@ -1,6 +1,6 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_RD(f32_to_ui64(f32(FRS1), RM, true)); +WRITE_RD(f32_to_ui64(FRS1_F, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h index 4033335..f3cd26e 100644 --- a/riscv/insns/fcvt_s_d.h +++ b/riscv/insns/fcvt_s_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_to_f32(f64(FRS1))); +WRITE_FRD_F(f64_to_f32(FRS1_D)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h index 22cdd72..346440a 100644 --- a/riscv/insns/fcvt_s_h.h +++ b/riscv/insns/fcvt_s_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFHMIN); +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_to_f32(f16(FRS1))); +WRITE_FRD_F(f16_to_f32(FRS1_H)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h index 9abcc80..1d096d2 100644 --- a/riscv/insns/fcvt_s_l.h +++ b/riscv/insns/fcvt_s_l.h @@ -1,6 +1,6 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i64_to_f32(RS1)); +WRITE_FRD_F(i64_to_f32(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h index 70c676e..e4e84cf 100644 --- a/riscv/insns/fcvt_s_lu.h +++ b/riscv/insns/fcvt_s_lu.h @@ -1,6 +1,6 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_rv64; require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui64_to_f32(RS1)); +WRITE_FRD_F(ui64_to_f32(RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h index 1ddabd8..75c87db 100644 --- a/riscv/insns/fcvt_s_w.h +++ b/riscv/insns/fcvt_s_w.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(i32_to_f32((int32_t)RS1)); +WRITE_FRD_F(i32_to_f32((int32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h index c1394c3..ec90fad 100644 --- a/riscv/insns/fcvt_s_wu.h +++ b/riscv/insns/fcvt_s_wu.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(ui32_to_f32((uint32_t)RS1)); +WRITE_FRD_F(ui32_to_f32((uint32_t)RS1)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h index 28eb245..a839f4b 100644 --- a/riscv/insns/fcvt_w_d.h +++ b/riscv/insns/fcvt_w_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true))); +WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h index fe8bb48..97e49a5 100644 --- a/riscv/insns/fcvt_w_h.h +++ b/riscv/insns/fcvt_w_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f16_to_i32(f16(FRS1), RM, true))); +WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h index d30f1b4..6aeb510 100644 --- a/riscv/insns/fcvt_w_s.h +++ b/riscv/insns/fcvt_w_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true))); +WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h index 5cdc004..906f003 100644 --- a/riscv/insns/fcvt_wu_d.h +++ b/riscv/insns/fcvt_wu_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true))); +WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h index bf6648d..ce11143 100644 --- a/riscv/insns/fcvt_wu_h.h +++ b/riscv/insns/fcvt_wu_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f16_to_ui32(f16(FRS1), RM, true))); +WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h index 034d681..a8b8455 100644 --- a/riscv/insns/fcvt_wu_s.h +++ b/riscv/insns/fcvt_wu_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true))); +WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true))); set_fp_exceptions; diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h index ae7911a..990afca 100644 --- a/riscv/insns/fdiv_d.h +++ b/riscv/insns/fdiv_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_div(f64(FRS1), f64(FRS2))); +WRITE_FRD_D(f64_div(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h index a169eae..91c518b 100644 --- a/riscv/insns/fdiv_h.h +++ b/riscv/insns/fdiv_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_div(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_div(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h index c74ff04..180b41d 100644 --- a/riscv/insns/fdiv_s.h +++ b/riscv/insns/fdiv_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_div(f32(FRS1), f32(FRS2))); +WRITE_FRD_F(f32_div(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h index 541ed5b..9585bad 100644 --- a/riscv/insns/feq_d.h +++ b/riscv/insns/feq_d.h @@ -1,4 +1,4 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_RD(f64_eq(f64(FRS1), f64(FRS2))); +WRITE_RD(f64_eq(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h index 47e75a5..5988db9 100644 --- a/riscv/insns/feq_h.h +++ b/riscv/insns/feq_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_RD(f16_eq(f16(FRS1), f16(FRS2))); +WRITE_RD(f16_eq(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h index 489bea6..97b57c2 100644 --- a/riscv/insns/feq_s.h +++ b/riscv/insns/feq_s.h @@ -1,4 +1,4 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_RD(f32_eq(f32(FRS1), f32(FRS2))); +WRITE_RD(f32_eq(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h index 419a36f..17b4932 100644 --- a/riscv/insns/fle_d.h +++ b/riscv/insns/fle_d.h @@ -1,4 +1,4 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_RD(f64_le(f64(FRS1), f64(FRS2))); +WRITE_RD(f64_le(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h index 9fc5968..31ed8a7 100644 --- a/riscv/insns/fle_h.h +++ b/riscv/insns/fle_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_RD(f16_le(f16(FRS1), f16(FRS2))); +WRITE_RD(f16_le(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h index 5c0124e..e26f055 100644 --- a/riscv/insns/fle_s.h +++ b/riscv/insns/fle_s.h @@ -1,4 +1,4 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_RD(f32_le(f32(FRS1), f32(FRS2))); +WRITE_RD(f32_le(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h index 7176a96..5fb0572 100644 --- a/riscv/insns/flt_d.h +++ b/riscv/insns/flt_d.h @@ -1,4 +1,4 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_RD(f64_lt(f64(FRS1), f64(FRS2))); +WRITE_RD(f64_lt(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h index f516a38..dd6bc79 100644 --- a/riscv/insns/flt_h.h +++ b/riscv/insns/flt_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_RD(f16_lt(f16(FRS1), f16(FRS2))); +WRITE_RD(f16_lt(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h index 40acc34..2f50ed6 100644 --- a/riscv/insns/flt_s.h +++ b/riscv/insns/flt_s.h @@ -1,4 +1,4 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_RD(f32_lt(f32(FRS1), f32(FRS2))); +WRITE_RD(f32_lt(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h index ab22beb..07a8b25 100644 --- a/riscv/insns/fmadd_d.h +++ b/riscv/insns/fmadd_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3))); +WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D)); set_fp_exceptions; diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h index 6551de5..5428897 100644 --- a/riscv/insns/fmadd_h.h +++ b/riscv/insns/fmadd_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(FRS3))); +WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H)); set_fp_exceptions; diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h index e919190..5a72cf8 100644 --- a/riscv/insns/fmadd_s.h +++ b/riscv/insns/fmadd_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3))); +WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F)); set_fp_exceptions; diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h index 11491f5..3e05b7e 100644 --- a/riscv/insns/fmax_d.h +++ b/riscv/insns/fmax_d.h @@ -1,9 +1,9 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) || - (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN)); -if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) - WRITE_FRD(f64(defaultNaNF64UI)); +bool greater = f64_lt_quiet(FRS2_D, FRS1_D) || + (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); else - WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD_D((greater || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h index 3d4c40e..c864258 100644 --- a/riscv/insns/fmax_h.h +++ b/riscv/insns/fmax_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_FRD(f16_max(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_max(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h index 41d8f92..17d8b3c 100644 --- a/riscv/insns/fmax_s.h +++ b/riscv/insns/fmax_s.h @@ -1,9 +1,9 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) || - (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN)); -if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) - WRITE_FRD(f32(defaultNaNF32UI)); +bool greater = f32_lt_quiet(FRS2_F, FRS1_F) || + (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); else - WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD_F((greater || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h index 5cf349d..f60a73e 100644 --- a/riscv/insns/fmin_d.h +++ b/riscv/insns/fmin_d.h @@ -1,9 +1,9 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) || - (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN)); -if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) - WRITE_FRD(f64(defaultNaNF64UI)); +bool less = f64_lt_quiet(FRS1_D, FRS2_D) || + (f64_eq(FRS1_D, FRS2_D) && (FRS1_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); else - WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD_D((less || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h index 5fb1404..cd02f20 100644 --- a/riscv/insns/fmin_h.h +++ b/riscv/insns/fmin_h.h @@ -1,4 +1,4 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_FRD(f16_min(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_min(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h index 19e1193..476a586 100644 --- a/riscv/insns/fmin_s.h +++ b/riscv/insns/fmin_s.h @@ -1,9 +1,9 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) || - (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN)); -if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) - WRITE_FRD(f32(defaultNaNF32UI)); +bool less = f32_lt_quiet(FRS1_F, FRS2_F) || + (f32_eq(FRS1_F, FRS2_F) && (FRS1_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); else - WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD_F((less || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h index 5b5bc0f..1a7d784 100644 --- a/riscv/insns/fmsub_d.h +++ b/riscv/insns/fmsub_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN))); +WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h index 934291f..dc6a8e6 100644 --- a/riscv/insns/fmsub_h.h +++ b/riscv/insns/fmsub_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN))); +WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h index d46c887..179cc2f 100644 --- a/riscv/insns/fmsub_s.h +++ b/riscv/insns/fmsub_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN))); +WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h index 9189d8d..e5caa34 100644 --- a/riscv/insns/fmul_d.h +++ b/riscv/insns/fmul_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2))); +WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h index 0152df8..dc7f9c4 100644 --- a/riscv/insns/fmul_h.h +++ b/riscv/insns/fmul_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_mul(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h index 145d5ce..9cf30b4 100644 --- a/riscv/insns/fmul_s.h +++ b/riscv/insns/fmul_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2))); +WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h index e8dd743..a2a14e9 100644 --- a/riscv/insns/fnmadd_d.h +++ b/riscv/insns/fnmadd_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN))); +WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h index e4c619e..b1ca283 100644 --- a/riscv/insns/fnmadd_h.h +++ b/riscv/insns/fnmadd_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN))); +WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h index 1c2996e..683257a 100644 --- a/riscv/insns/fnmadd_s.h +++ b/riscv/insns/fnmadd_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN))); +WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h index c29a0b9..9352c3f 100644 --- a/riscv/insns/fnmsub_d.h +++ b/riscv/insns/fnmsub_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3))); +WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D)); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h index 0410c3b..e05fcd1 100644 --- a/riscv/insns/fnmsub_h.h +++ b/riscv/insns/fnmsub_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(FRS3))); +WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H)); set_fp_exceptions; diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h index 4c61fc7..b22b3db 100644 --- a/riscv/insns/fnmsub_s.h +++ b/riscv/insns/fnmsub_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3))); +WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F)); set_fp_exceptions; diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h index 78f9ce7..8f02fd1 100644 --- a/riscv/insns/fsgnj_d.h +++ b/riscv/insns/fsgnj_d.h @@ -1,3 +1,3 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_FRD(fsgnj64(FRS1, FRS2, false, false)); +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false)); diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h index 79d50f5..080f27d 100644 --- a/riscv/insns/fsgnj_h.h +++ b/riscv/insns/fsgnj_h.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_FRD(fsgnj16(FRS1, FRS2, false, false)); +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false)); diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h index c1a70cb..ea511b8 100644 --- a/riscv/insns/fsgnj_s.h +++ b/riscv/insns/fsgnj_s.h @@ -1,3 +1,3 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_FRD(fsgnj32(FRS1, FRS2, false, false)); +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false)); diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h index f02c311..870a979 100644 --- a/riscv/insns/fsgnjn_d.h +++ b/riscv/insns/fsgnjn_d.h @@ -1,3 +1,3 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_FRD(fsgnj64(FRS1, FRS2, true, false)); +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false)); diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h index ebb4ac9..1d7bf03 100644 --- a/riscv/insns/fsgnjn_h.h +++ b/riscv/insns/fsgnjn_h.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_FRD(fsgnj16(FRS1, FRS2, true, false)); +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false)); \ No newline at end of file diff --git a/riscv/insns/fsgnjn_q.h b/riscv/insns/fsgnjn_q.h index 38c7bbf..dcf7235 100644 --- a/riscv/insns/fsgnjn_q.h +++ b/riscv/insns/fsgnjn_q.h @@ -1,3 +1,3 @@ require_extension('Q'); require_fp; -WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); +WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); \ No newline at end of file diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h index 35906d6..a0994b4 100644 --- a/riscv/insns/fsgnjn_s.h +++ b/riscv/insns/fsgnjn_s.h @@ -1,3 +1,3 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_FRD(fsgnj32(FRS1, FRS2, true, false)); +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false)); diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h index c121737..25906f0 100644 --- a/riscv/insns/fsgnjx_d.h +++ b/riscv/insns/fsgnjx_d.h @@ -1,3 +1,3 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; -WRITE_FRD(fsgnj64(FRS1, FRS2, false, true)); +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true)); diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h index 9310269..1d29bb1 100644 --- a/riscv/insns/fsgnjx_h.h +++ b/riscv/insns/fsgnjx_h.h @@ -1,3 +1,3 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; -WRITE_FRD(fsgnj16(FRS1, FRS2, false, true)); +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true)); diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h index 4d5c624..9bc0798 100644 --- a/riscv/insns/fsgnjx_s.h +++ b/riscv/insns/fsgnjx_s.h @@ -1,3 +1,3 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; -WRITE_FRD(fsgnj32(FRS1, FRS2, false, true)); +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true)); diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h index da138ba..363b457 100644 --- a/riscv/insns/fsqrt_d.h +++ b/riscv/insns/fsqrt_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_sqrt(f64(FRS1))); +WRITE_FRD_D(f64_sqrt(FRS1_D)); set_fp_exceptions; diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h index 138d572..fea429b 100644 --- a/riscv/insns/fsqrt_h.h +++ b/riscv/insns/fsqrt_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_sqrt(f16(FRS1))); +WRITE_FRD_H(f16_sqrt(FRS1_H)); set_fp_exceptions; diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h index 7476846..d44503a 100644 --- a/riscv/insns/fsqrt_s.h +++ b/riscv/insns/fsqrt_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_sqrt(f32(FRS1))); +WRITE_FRD_F(f32_sqrt(FRS1_F)); set_fp_exceptions; diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h index 1418a06..4f8bf50 100644 --- a/riscv/insns/fsub_d.h +++ b/riscv/insns/fsub_d.h @@ -1,5 +1,5 @@ -require_extension('D'); +require_either_extension('D', EXT_ZDINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2))); +WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D)); set_fp_exceptions; diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h index 43b51cc..f7006fb 100644 --- a/riscv/insns/fsub_h.h +++ b/riscv/insns/fsub_h.h @@ -1,5 +1,5 @@ -require_extension(EXT_ZFH); +require_either_extension(EXT_ZFH, EXT_ZHINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2))); +WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H)); set_fp_exceptions; diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h index f6183ea..1a33ffd 100644 --- a/riscv/insns/fsub_s.h +++ b/riscv/insns/fsub_s.h @@ -1,5 +1,5 @@ -require_extension('F'); +require_either_extension('F', EXT_ZFINX); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2))); +WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F)); set_fp_exceptions; diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h index 66eeacc..40f3c18 100644 --- a/riscv/insns/vfslide1down_vf.h +++ b/riscv/insns/vfslide1down_vf.h @@ -23,13 +23,13 @@ if (i != vl - 1) { } else { switch (P.VU.vsew) { case e16: - P.VU.elt(rd_num, vl - 1, true) = f16(FRS1); + P.VU.elt(rd_num, vl - 1, true) = FRS1_H; break; case e32: - P.VU.elt(rd_num, vl - 1, true) = f32(FRS1); + P.VU.elt(rd_num, vl - 1, true) = FRS1_F; break; case e64: - P.VU.elt(rd_num, vl - 1, true) = f64(FRS1); + P.VU.elt(rd_num, vl - 1, true) = FRS1_D; break; } } diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h index b9c2817..4e4e499 100644 --- a/riscv/insns/vfslide1up_vf.h +++ b/riscv/insns/vfslide1up_vf.h @@ -23,13 +23,13 @@ if (i != 0) { } else { switch (P.VU.vsew) { case e16: - P.VU.elt(rd_num, 0, true) = f16(FRS1); + P.VU.elt(rd_num, 0, true) = FRS1_H; break; case e32: - P.VU.elt(rd_num, 0, true) = f32(FRS1); + P.VU.elt(rd_num, 0, true) = FRS1_F; break; case e64: - P.VU.elt(rd_num, 0, true) = f64(FRS1); + P.VU.elt(rd_num, 0, true) = FRS1_D; break; } } -- cgit v1.1 From ce34edb0eecec520d6d2cfec5bda57ca90a69f14 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 10 Aug 2022 22:55:07 +0800 Subject: Add space between if/while/switch and '(' Add space between ')' and '{' --- riscv/insns/aes64ks1i.h | 4 ++-- riscv/insns/beq.h | 2 +- riscv/insns/bge.h | 2 +- riscv/insns/bgeu.h | 2 +- riscv/insns/blt.h | 2 +- riscv/insns/bltu.h | 2 +- riscv/insns/bne.h | 2 +- riscv/insns/div.h | 4 ++-- riscv/insns/divu.h | 2 +- riscv/insns/divuw.h | 2 +- riscv/insns/divw.h | 2 +- riscv/insns/kmmawb2.h | 2 +- riscv/insns/kmmawb2_u.h | 2 +- riscv/insns/kmmawt2.h | 2 +- riscv/insns/kmmawt2_u.h | 2 +- riscv/insns/kmmwb2.h | 2 +- riscv/insns/kmmwb2_u.h | 2 +- riscv/insns/kmmwt2.h | 2 +- riscv/insns/kmmwt2_u.h | 2 +- riscv/insns/kslra16_u.h | 2 +- riscv/insns/kslra32_u.h | 2 +- riscv/insns/kslra8_u.h | 2 +- riscv/insns/kwmmul.h | 2 +- riscv/insns/kwmmul_u.h | 2 +- riscv/insns/rem.h | 4 ++-- riscv/insns/remu.h | 2 +- riscv/insns/remuw.h | 2 +- riscv/insns/remw.h | 2 +- riscv/insns/rsub64.h | 2 +- riscv/insns/sra16_u.h | 2 +- riscv/insns/sra32_u.h | 2 +- riscv/insns/sra8_u.h | 2 +- riscv/insns/vdiv_vx.h | 4 ++-- riscv/insns/vdivu_vv.h | 2 +- riscv/insns/vdivu_vx.h | 2 +- riscv/insns/vfmv_f_s.h | 2 +- riscv/insns/vfmv_s_f.h | 2 +- riscv/insns/vmsbf_m.h | 2 +- riscv/insns/vmsif_m.h | 2 +- riscv/insns/vmsof_m.h | 2 +- riscv/insns/vmv_s_x.h | 2 +- riscv/insns/vmv_x_s.h | 2 +- riscv/insns/vrem_vv.h | 2 +- riscv/insns/vsadd_vi.h | 2 +- riscv/insns/vsadd_vv.h | 2 +- riscv/insns/vsadd_vx.h | 2 +- riscv/insns/vslide1up_vx.h | 12 ++++++------ 47 files changed, 56 insertions(+), 56 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index fff7109..3ce3c3f 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,7 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if(enc_rcon > 0xA) { +if (enc_rcon > 0xA) { // Invalid opcode. throw trap_illegal_instruction(0); } @@ -19,7 +19,7 @@ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; uint64_t result ; -if(enc_rcon != 0xA) { +if (enc_rcon != 0xA) { temp = (temp >> 8) | (temp << 24); // Rotate right by 8 rcon = round_consts[enc_rcon]; } diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h index fd7e061..3d2c975 100644 --- a/riscv/insns/beq.h +++ b/riscv/insns/beq.h @@ -1,2 +1,2 @@ -if(RS1 == RS2) +if (RS1 == RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h index da0c68e..b2421c2 100644 --- a/riscv/insns/bge.h +++ b/riscv/insns/bge.h @@ -1,2 +1,2 @@ -if(sreg_t(RS1) >= sreg_t(RS2)) +if (sreg_t(RS1) >= sreg_t(RS2)) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h index d764a34..f09b7f4 100644 --- a/riscv/insns/bgeu.h +++ b/riscv/insns/bgeu.h @@ -1,2 +1,2 @@ -if(RS1 >= RS2) +if (RS1 >= RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h index c54fb76..cad064b 100644 --- a/riscv/insns/blt.h +++ b/riscv/insns/blt.h @@ -1,2 +1,2 @@ -if(sreg_t(RS1) < sreg_t(RS2)) +if (sreg_t(RS1) < sreg_t(RS2)) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h index ff75e8a..b7c3300 100644 --- a/riscv/insns/bltu.h +++ b/riscv/insns/bltu.h @@ -1,2 +1,2 @@ -if(RS1 < RS2) +if (RS1 < RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h index 1e6cb7c..e832fa1 100644 --- a/riscv/insns/bne.h +++ b/riscv/insns/bne.h @@ -1,2 +1,2 @@ -if(RS1 != RS2) +if (RS1 != RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/div.h b/riscv/insns/div.h index 9cbe8d6..fb62437 100644 --- a/riscv/insns/div.h +++ b/riscv/insns/div.h @@ -1,9 +1,9 @@ require_extension('M'); sreg_t lhs = sext_xlen(RS1); sreg_t rhs = sext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); -else if(lhs == INT64_MIN && rhs == -1) +else if (lhs == INT64_MIN && rhs == -1) WRITE_RD(lhs); else WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h index 31d7585..ed05818 100644 --- a/riscv/insns/divu.h +++ b/riscv/insns/divu.h @@ -1,7 +1,7 @@ require_extension('M'); reg_t lhs = zext_xlen(RS1); reg_t rhs = zext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h index e127619..bc7e9d2 100644 --- a/riscv/insns/divuw.h +++ b/riscv/insns/divuw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; reg_t lhs = zext32(RS1); reg_t rhs = zext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext32(lhs / rhs)); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h index 11be17e..54409b0 100644 --- a/riscv/insns/divw.h +++ b/riscv/insns/divw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; sreg_t lhs = sext32(RS1); sreg_t rhs = sext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext32(lhs / rhs)); diff --git a/riscv/insns/kmmawb2.h b/riscv/insns/kmmawb2.h index 6b3aa0d..274f9dd 100644 --- a/riscv/insns/kmmawb2.h +++ b/riscv/insns/kmmawb2.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; addop = mres >> 16; } else { diff --git a/riscv/insns/kmmawb2_u.h b/riscv/insns/kmmawb2_u.h index f44346e..447a3f4 100644 --- a/riscv/insns/kmmawb2_u.h +++ b/riscv/insns/kmmawb2_u.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; addop = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmawt2.h b/riscv/insns/kmmawt2.h index 3cd72de..6eb22ac 100644 --- a/riscv/insns/kmmawt2.h +++ b/riscv/insns/kmmawt2.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; addop = mres >> 16; } else { diff --git a/riscv/insns/kmmawt2_u.h b/riscv/insns/kmmawt2_u.h index 7fe378c..b82e090 100644 --- a/riscv/insns/kmmawt2_u.h +++ b/riscv/insns/kmmawt2_u.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; addop = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmwb2.h b/riscv/insns/kmmwb2.h index 272f738..d08b0ef 100644 --- a/riscv/insns/kmmwb2.h +++ b/riscv/insns/kmmwb2.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; pd = mres >> 16; } else { diff --git a/riscv/insns/kmmwb2_u.h b/riscv/insns/kmmwb2_u.h index b5a5006..d308bf3 100644 --- a/riscv/insns/kmmwb2_u.h +++ b/riscv/insns/kmmwb2_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; pd = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmwt2.h b/riscv/insns/kmmwt2.h index 73d3dc8..38ba9b1 100644 --- a/riscv/insns/kmmwt2.h +++ b/riscv/insns/kmmwt2.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; pd = mres >> 16; } else { diff --git a/riscv/insns/kmmwt2_u.h b/riscv/insns/kmmwt2_u.h index 1f525a8..e855786 100644 --- a/riscv/insns/kmmwt2_u.h +++ b/riscv/insns/kmmwt2_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; pd = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kslra16_u.h b/riscv/insns/kslra16_u.h index 8335f3e..27bb77c 100644 --- a/riscv/insns/kslra16_u.h +++ b/riscv/insns/kslra16_u.h @@ -3,7 +3,7 @@ P_X_LOOP(16, 5, { if (ssa < 0) { sa = -ssa; sa = (sa == 16) ? 15 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kslra32_u.h b/riscv/insns/kslra32_u.h index d53c8fe..b9c06cf 100644 --- a/riscv/insns/kslra32_u.h +++ b/riscv/insns/kslra32_u.h @@ -4,7 +4,7 @@ P_X_LOOP(32, 6, { if (ssa < 0) { sa = -ssa; sa = (sa == 32) ? 31 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kslra8_u.h b/riscv/insns/kslra8_u.h index 620f3bd..340283f 100644 --- a/riscv/insns/kslra8_u.h +++ b/riscv/insns/kslra8_u.h @@ -3,7 +3,7 @@ P_X_LOOP(8, 4, { if (ssa < 0) { sa = -ssa; sa = (sa == 8) ? 7 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kwmmul.h b/riscv/insns/kwmmul.h index b0ab8d4..ca654f2 100644 --- a/riscv/insns/kwmmul.h +++ b/riscv/insns/kwmmul.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; pd = mres >> 32; } else { diff --git a/riscv/insns/kwmmul_u.h b/riscv/insns/kwmmul_u.h index c2045e1..b435561 100644 --- a/riscv/insns/kwmmul_u.h +++ b/riscv/insns/kwmmul_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; pd = ((mres >> 31) + 1) >> 1; } else { diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h index 8587995..d2ee066 100644 --- a/riscv/insns/rem.h +++ b/riscv/insns/rem.h @@ -1,9 +1,9 @@ require_extension('M'); sreg_t lhs = sext_xlen(RS1); sreg_t rhs = sext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(lhs); -else if(lhs == INT64_MIN && rhs == -1) +else if (lhs == INT64_MIN && rhs == -1) WRITE_RD(0); else WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h index e74774c..676747a 100644 --- a/riscv/insns/remu.h +++ b/riscv/insns/remu.h @@ -1,7 +1,7 @@ require_extension('M'); reg_t lhs = zext_xlen(RS1); reg_t rhs = zext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(sext_xlen(RS1)); else WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h index b239c8f..caa1583 100644 --- a/riscv/insns/remuw.h +++ b/riscv/insns/remuw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; reg_t lhs = zext32(RS1); reg_t rhs = zext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(sext32(lhs)); else WRITE_RD(sext32(lhs % rhs)); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h index 56221cc..076096c 100644 --- a/riscv/insns/remw.h +++ b/riscv/insns/remw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; sreg_t lhs = sext32(RS1); sreg_t rhs = sext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(lhs); else WRITE_RD(sext32(lhs % rhs)); diff --git a/riscv/insns/rsub64.h b/riscv/insns/rsub64.h index 397c973..2a58485 100644 --- a/riscv/insns/rsub64.h +++ b/riscv/insns/rsub64.h @@ -2,7 +2,7 @@ P_64_PROFILE({ rd = (rs1 - rs2) >> 1; if (rs1 > 0 && rs2 < 0) { rd &= ~((reg_t)1 << 63); - } else if(rs1 < 0 && rs2 > 0) { + } else if (rs1 < 0 && rs2 > 0) { rd |= ((reg_t)1 << 63); } }) diff --git a/riscv/insns/sra16_u.h b/riscv/insns/sra16_u.h index c28178e..6fcc398 100644 --- a/riscv/insns/sra16_u.h +++ b/riscv/insns/sra16_u.h @@ -1,5 +1,5 @@ P_X_LOOP(16, 4, { - if(sa > 0) + if (sa > 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/sra32_u.h b/riscv/insns/sra32_u.h index e062a88..1a4488c 100644 --- a/riscv/insns/sra32_u.h +++ b/riscv/insns/sra32_u.h @@ -1,6 +1,6 @@ require_rv64; P_X_LOOP(32, 5, { - if(sa > 0) + if (sa > 0) pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/sra8_u.h b/riscv/insns/sra8_u.h index 7061fc4..1f47623 100644 --- a/riscv/insns/sra8_u.h +++ b/riscv/insns/sra8_u.h @@ -1,5 +1,5 @@ P_X_LOOP(8, 3, { - if(sa > 0) + if (sa > 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h index 4052952..2b93eac 100644 --- a/riscv/insns/vdiv_vx.h +++ b/riscv/insns/vdiv_vx.h @@ -1,9 +1,9 @@ // vdiv.vx vd, vs2, rs1 VI_VX_LOOP ({ - if(rs1 == 0) + if (rs1 == 0) vd = -1; - else if(vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) + else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) vd = vs2; else vd = vs2 / rs1; diff --git a/riscv/insns/vdivu_vv.h b/riscv/insns/vdivu_vv.h index ef6e777..89aeed6 100644 --- a/riscv/insns/vdivu_vv.h +++ b/riscv/insns/vdivu_vv.h @@ -1,7 +1,7 @@ // vdivu.vv vd, vs2, vs1 VI_VV_ULOOP ({ - if(vs1 == 0) + if (vs1 == 0) vd = -1; else vd = vs2 / vs1; diff --git a/riscv/insns/vdivu_vx.h b/riscv/insns/vdivu_vx.h index 7ffe1c6..ce3e964 100644 --- a/riscv/insns/vdivu_vx.h +++ b/riscv/insns/vdivu_vx.h @@ -1,7 +1,7 @@ // vdivu.vx vd, vs2, rs1 VI_VX_ULOOP ({ - if(rs1 == 0) + if (rs1 == 0) vd = -1; else vd = vs2 / rs1; diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 81605ea..0f3cf8c 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -9,7 +9,7 @@ require(STATE.frm->read() < 0x5); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; const reg_t sew = P.VU.vsew; -switch(sew) { +switch (sew) { case e16: vs2_0 = P.VU.elt(rs2_num, 0); break; diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index edc376e..e50ad41 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -11,7 +11,7 @@ reg_t vl = P.VU.vl->read(); if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); - switch(P.VU.vsew) { + switch (P.VU.vsew) { case e16: P.VU.elt(rd_num, 0, true) = f16(FRS1).v; break; diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 6147f6d..1275872 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -24,7 +24,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { uint64_t res = 0; if (!has_one && !vs2_lsb) { res = 1; - } else if(!has_one && vs2_lsb) { + } else if (!has_one && vs2_lsb) { has_one = true; } vd = (vd & ~mmask) | ((res << mpos) & mmask); diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 447813f..cbcbc2a 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -23,7 +23,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { uint64_t res = 0; if (!has_one && !vs2_lsb) { res = 1; - } else if(!has_one && vs2_lsb) { + } else if (!has_one && vs2_lsb) { has_one = true; res = 1; } diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index b9edcf3..9bd4f0c 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -21,7 +21,7 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) { if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { uint64_t &vd = P.VU.elt(rd_num, midx, true); uint64_t res = 0; - if(!has_one && vs2_lsb) { + if (!has_one && vs2_lsb) { has_one = true; res = 1; } diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index b66855b..23a6b56 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -8,7 +8,7 @@ if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); reg_t sew = P.VU.vsew; - switch(sew) { + switch (sew) { case e8: P.VU.elt(rd_num, 0, true) = RS1; break; diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index d33c3e5..8451d6a 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -6,7 +6,7 @@ reg_t rs1 = RS1; reg_t sew = P.VU.vsew; reg_t rs2_num = insn.rs2(); -switch(sew) { +switch (sew) { case e8: WRITE_RD(P.VU.elt(rs2_num, 0)); break; diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index 260716a..5c58fa4 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = vs2; - else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) vd = 0; else { vd = vs2 % vs1; diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index 7e3b652..3a8b1d4 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VI_PARAMS(e8); vd = sat_add(vs2, vsext(simm5, sew), sat); diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 60ad5f3..d4cfe78 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VV_PARAMS(e8); vd = sat_add(vs2, vs1, sat); diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h index bf68f15..e5e6c40 100644 --- a/riscv/insns/vsadd_vx.h +++ b/riscv/insns/vsadd_vx.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VX_PARAMS(e8); vd = sat_add(vs2, rs1, sat); diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 33cb9ed..256419e 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -6,24 +6,24 @@ if (i != 0) { if (sew == e8) { VI_XI_SLIDEUP_PARAMS(e8, 1); vd = vs2; - } else if(sew == e16) { + } else if (sew == e16) { VI_XI_SLIDEUP_PARAMS(e16, 1); vd = vs2; - } else if(sew == e32) { + } else if (sew == e32) { VI_XI_SLIDEUP_PARAMS(e32, 1); vd = vs2; - } else if(sew == e64) { + } else if (sew == e64) { VI_XI_SLIDEUP_PARAMS(e64, 1); vd = vs2; } } else { if (sew == e8) { P.VU.elt(rd_num, 0, true) = RS1; - } else if(sew == e16) { + } else if (sew == e16) { P.VU.elt(rd_num, 0, true) = RS1; - } else if(sew == e32) { + } else if (sew == e32) { P.VU.elt(rd_num, 0, true) = RS1; - } else if(sew == e64) { + } else if (sew == e64) { P.VU.elt(rd_num, 0, true) = RS1; } } -- cgit v1.1 From 6aa46e99c36f1bf394b3f7fae3c729e8b7918a80 Mon Sep 17 00:00:00 2001 From: ksco Date: Sat, 13 Aug 2022 04:37:26 +0800 Subject: Remove unused code in vsmul* (#1069) --- riscv/insns/vsmul_vv.h | 12 ++---------- riscv/insns/vsmul_vx.h | 9 --------- 2 files changed, 2 insertions(+), 19 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index 413981c..49e42c1 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -2,27 +2,19 @@ VRM xrm = P.VU.get_vround_mode(); int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); -int64_t sign_mask = uint64_t(1) << (P.VU.vsew - 1); VI_VV_LOOP ({ - int64_t vs1_sign; - int64_t vs2_sign; - int64_t result_sign; - - vs1_sign = vs1 & sign_mask; - vs2_sign = vs2 & sign_mask; bool overflow = vs1 == vs2 && vs1 == int_min; - int128_t result = (int128_t)vs1 * (int128_t)vs2; - result_sign = (vs1_sign ^ vs2_sign) & sign_mask; // rounding INT_ROUNDING(result, xrm, sew - 1); + // remove guard bits result = result >> (sew - 1); - // saturation + // max saturation if (overflow) { result = int_max; P_SET_OV(1); diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h index 2e25670..d2724ee 100644 --- a/riscv/insns/vsmul_vx.h +++ b/riscv/insns/vsmul_vx.h @@ -2,20 +2,11 @@ VRM xrm = P.VU.get_vround_mode(); int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); -int64_t sign_mask = uint64_t(1) << (P.VU.vsew - 1); VI_VX_LOOP ({ - int64_t rs1_sign; - int64_t vs2_sign; - int64_t result_sign; - - rs1_sign = rs1 & sign_mask; - vs2_sign = vs2 & sign_mask; bool overflow = rs1 == vs2 && rs1 == int_min; - int128_t result = (int128_t)rs1 * (int128_t)vs2; - result_sign = (rs1_sign ^ vs2_sign) & sign_mask; // rounding INT_ROUNDING(result, xrm, sew - 1); -- cgit v1.1 From 1556cf7fe2d8e31ca9e80b8e6e9eea7fbf12314d Mon Sep 17 00:00:00 2001 From: yangcheng <28107329+yorange1@users.noreply.github.com> Date: Tue, 23 Aug 2022 05:05:19 +0800 Subject: Fix redundant loops when calculating vrgather.vi. (#1072) --- riscv/insns/vrgather_vi.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h index 56e11e1..85ba621 100644 --- a/riscv/insns/vrgather_vi.h +++ b/riscv/insns/vrgather_vi.h @@ -7,10 +7,6 @@ require_vm; reg_t zimm5 = insn.v_zimm5(); VI_LOOP_BASE - -for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { - VI_LOOP_ELEMENT_SKIP(); - switch (sew) { case e8: P.VU.elt(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt(rs2_num, zimm5); @@ -25,6 +21,4 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { P.VU.elt(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt(rs2_num, zimm5); break; } -} - VI_LOOP_END; -- cgit v1.1 From 4d515ade6ef853f505e168d05e964f04b1bd938f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Sep 2022 15:48:11 -0700 Subject: vmvr.v depends on vtype, and therefore should check vill --- riscv/insns/vmvnfr_v.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index f6dc2c0..1dc304a 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,5 +1,5 @@ // vmv1r.v vd, vs2 -require_vector_novtype(true, true); +require_vector(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); const reg_t vs2 = insn.rs2(); -- cgit v1.1 From 503b0106d7a328d9aa4282186fa48436b389e934 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Sep 2022 15:49:18 -0700 Subject: fix comment in definition of vmvr.v --- riscv/insns/vmvnfr_v.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index 1dc304a..543ac58 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,4 +1,4 @@ -// vmv1r.v vd, vs2 +// vmvr.v vd, vs2 require_vector(true); const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); -- cgit v1.1 From d85446f81f3c9405a2041ab5235281a3bbaab77f Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Thu, 8 Sep 2022 21:16:35 +0800 Subject: Remove unnecessary argument alu(always false) from macro require_vector_novtype --- riscv/insns/vsetivli.h | 2 +- riscv/insns/vsetvl.h | 2 +- riscv/insns/vsetvli.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vsetivli.h b/riscv/insns/vsetivli.h index 04900a2..f880e96 100644 --- a/riscv/insns/vsetivli.h +++ b/riscv/insns/vsetivli.h @@ -1,2 +1,2 @@ -require_vector_novtype(false, false); +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index 2969edc..4d03542 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1,2 +1,2 @@ -require_vector_novtype(false, false); +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index 7b1f1d7..d1f43b5 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1,2 +1,2 @@ -require_vector_novtype(false, false); +require_vector_novtype(false); WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); -- cgit v1.1 From 55c66198fd6bc8f1b16e67a33d2865ca3e7269cb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 28 Sep 2022 01:06:53 -0700 Subject: Fix vmv.x.s for RV32 The Spike internals require that, when XLEN is narrower than reg_t, values be sign-extended to the width of reg_t. --- riscv/insns/vmv_x_s.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 8451d6a..16153eb 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -1,27 +1,28 @@ // vmv_x_s: rd = vs2[0] require_vector(true); require(insn.v_vm() == 1); -uint64_t xmask = UINT64_MAX >> (64 - P.get_isa().get_max_xlen()); reg_t rs1 = RS1; reg_t sew = P.VU.vsew; reg_t rs2_num = insn.rs2(); +reg_t res; switch (sew) { case e8: - WRITE_RD(P.VU.elt(rs2_num, 0)); + res = P.VU.elt(rs2_num, 0); break; case e16: - WRITE_RD(P.VU.elt(rs2_num, 0)); + res = P.VU.elt(rs2_num, 0); break; case e32: - WRITE_RD(P.VU.elt(rs2_num, 0)); + res = P.VU.elt(rs2_num, 0); break; case e64: - if (P.get_isa().get_max_xlen() <= sew) - WRITE_RD(P.VU.elt(rs2_num, 0) & xmask); - else - WRITE_RD(P.VU.elt(rs2_num, 0)); + res = P.VU.elt(rs2_num, 0); break; +default: + abort(); } +WRITE_RD(sext_xlen(res)); + P.VU.vstart->write(0); -- cgit v1.1 From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 17:34:33 -0700 Subject: Suppress most unused variable warnings --- riscv/insns/amoswap_d.h | 2 +- riscv/insns/amoswap_w.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h index e1bffde..f9188ea 100644 --- a/riscv/insns/amoswap_d.h +++ b/riscv/insns/amoswap_d.h @@ -1,3 +1,3 @@ require_extension('A'); require_rv64; -WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; })); +WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t UNUSED lhs) { return RS2; })); diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h index 0f78369..151f095 100644 --- a/riscv/insns/amoswap_w.h +++ b/riscv/insns/amoswap_w.h @@ -1,2 +1,2 @@ require_extension('A'); -WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; }))); +WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t UNUSED lhs) { return RS2; }))); -- cgit v1.1 From d2f34d1e41a7d2884aec4d1d3daa1dbf549d059e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 18:34:45 -0700 Subject: Suppress unused-variable warnings in AES code --- riscv/insns/aes_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/aes_common.h b/riscv/insns/aes_common.h index 9cc353c..4f3f618 100644 --- a/riscv/insns/aes_common.h +++ b/riscv/insns/aes_common.h @@ -1,5 +1,5 @@ -uint8_t AES_ENC_SBOX[]= { +static uint8_t UNUSED AES_ENC_SBOX[]= { 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, @@ -34,7 +34,7 @@ uint8_t AES_ENC_SBOX[]= { 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 }; -uint8_t AES_DEC_SBOX[] = { +static uint8_t UNUSED AES_DEC_SBOX[] = { 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, -- cgit v1.1 From e2139a5d1c11954ede663539c8666e8696474c01 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 18:35:12 -0700 Subject: Suppress unused-variable warnings in vector instruction definitions --- riscv/insns/vcpop_m.h | 2 -- riscv/insns/vfirst_m.h | 2 -- riscv/insns/vid_v.h | 3 --- riscv/insns/viota_m.h | 1 - riscv/insns/vmv_x_s.h | 1 - riscv/insns/vmvnfr_v.h | 1 - 6 files changed, 10 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h index cbe45a4..671362f 100644 --- a/riscv/insns/vcpop_m.h +++ b/riscv/insns/vcpop_m.h @@ -2,8 +2,6 @@ require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); reg_t vl = P.VU.vl->read(); -reg_t sew = P.VU.vsew; -reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); require(P.VU.vstart->read() == 0); reg_t popcount = 0; diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h index 5b768ed..9ddc82b 100644 --- a/riscv/insns/vfirst_m.h +++ b/riscv/insns/vfirst_m.h @@ -2,8 +2,6 @@ require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); reg_t vl = P.VU.vl->read(); -reg_t sew = P.VU.vsew; -reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); require(P.VU.vstart->read() == 0); reg_t pos = -1; diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index c316291..510132d 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -1,11 +1,8 @@ // vmpopc rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); -reg_t rs1_num = insn.rs1(); -reg_t rs2_num = insn.rs2(); require_align(rd_num, P.VU.vflmul); require_vm; diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h index f74f2c2..1ee9229 100644 --- a/riscv/insns/viota_m.h +++ b/riscv/insns/viota_m.h @@ -4,7 +4,6 @@ require_vector(true); reg_t vl = P.VU.vl->read(); reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); -reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); require(P.VU.vstart->read() == 0); require_vm; diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index 16153eb..57a9e1a 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -1,7 +1,6 @@ // vmv_x_s: rd = vs2[0] require_vector(true); require(insn.v_vm() == 1); -reg_t rs1 = RS1; reg_t sew = P.VU.vsew; reg_t rs2_num = insn.rs2(); reg_t res; diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index 543ac58..9c52810 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,6 +1,5 @@ // vmvr.v vd, vs2 require_vector(true); -const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); const reg_t vs2 = insn.rs2(); const reg_t len = insn.rs1() + 1; -- cgit v1.1 From 258a0c62eb400380d72fade82e154a4bd2af9b83 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 18:41:02 -0700 Subject: Fix unused-variable warnings in P-extension instruction definitions --- riscv/insns/kmar64.h | 1 - 1 file changed, 1 deletion(-) (limited to 'riscv/insns') diff --git a/riscv/insns/kmar64.h b/riscv/insns/kmar64.h index 49f4482..a4d332b 100644 --- a/riscv/insns/kmar64.h +++ b/riscv/insns/kmar64.h @@ -5,7 +5,6 @@ P_64_PROFILE_PARAM(true, false) bool sat = false; sreg_t mres0 = (sreg_t)P_SW(rs1, 0) * P_SW(rs2, 0); sreg_t mres1 = (sreg_t)P_SW(rs1, 1) * P_SW(rs2, 1); -sreg_t res; if (xlen == 32) { rd = (sat_add(rd, mres0, sat)); -- cgit v1.1 From 86d9fe49eda1fff863a43e682015216a25cc72f3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Oct 2022 15:19:00 -0700 Subject: Set tval on illegal subforms of aes64ks1i h/t @YenHaoChen --- riscv/insns/aes64ks1i.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'riscv/insns') diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index 3ce3c3f..c7354d6 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,10 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if (enc_rcon > 0xA) { - // Invalid opcode. - throw trap_illegal_instruction(0); -} +require(enc_rcon <= 0xA); uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; -- cgit v1.1