From f5a68933e509620326d6ff90b449dd074ae915ea Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Tue, 22 Oct 2019 21:36:05 -0700 Subject: rvv: add reg checking rule for general fomrat for most instruction which are in single, single, single/scalar/immediate format Signed-off-by: Chih-Min Chao --- riscv/insns/vsadd_vi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/insns/vsadd_vi.h') diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index de2cb83..c361f08 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -1,4 +1,5 @@ // vsadd.vi vd, vs2 simm5 +VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; switch(sew) { -- cgit v1.1