From 5a208b28a23fa408d12f91f838564575a4270043 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 23 Mar 2020 20:27:28 -0700 Subject: rvv: restrict segment load register rule For unit-strided and stride segment load, mask register can't overlap destination register if masked ref: https://github.com/riscv/riscv-v-spec/pull/395 Signed-off-by: Chih-Min Chao --- riscv/insns/vmerge_vvm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/insns/vmerge_vvm.h') diff --git a/riscv/insns/vmerge_vvm.h b/riscv/insns/vmerge_vvm.h index 97a0182..f0a3fd5 100644 --- a/riscv/insns/vmerge_vvm.h +++ b/riscv/insns/vmerge_vvm.h @@ -1,4 +1,5 @@ // vmerge.vvm vd, vs2, vs1 +require_vector; VI_CHECK_SSS(true); VI_VVXI_MERGE_LOOP ({ -- cgit v1.1