From 5de0c89c034cf64fdab8e36d2dc7488aa035d823 Mon Sep 17 00:00:00 2001
From: liweiwei <liweiwei@iscas.ac.cn>
Date: Thu, 14 Oct 2021 09:49:10 +0800
Subject: Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min}
 instructions

change the extention check for F/D/Zfh instructions

modify the F/D/Zfh instructions to read X regs when enable Zfinx

Co-authored-by: wangmeng <shusheng8495@hotmail.com>
---
 riscv/insns/vfslide1up_vf.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'riscv/insns/vfslide1up_vf.h')

diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h
index b9c2817..4e4e499 100644
--- a/riscv/insns/vfslide1up_vf.h
+++ b/riscv/insns/vfslide1up_vf.h
@@ -23,13 +23,13 @@ if (i != 0) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, 0, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, 0, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, 0, true) = FRS1_D;
       break;
   }
 }
-- 
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